Patents by Inventor Chia-Yun Chen

Chia-Yun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7132354
    Abstract: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the substrate, a blanket dielectric layer overlying the substrate and gate electrodes, and a plurality of polycrystalline silicon plugs, respectively disposed on the substrate between the gate electrodes, in the dielectric layer. A piping defect is detected by the analysis image showing an area with voltage contrast difference.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 7, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Long-Hui Lin, Hsien-Te Lo, Chia-Yun Chen
  • Publication number: 20060134812
    Abstract: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the substrate, a blanket dielectric layer overlying the substrate and gate electrodes, and a plurality of polycrystalline silicon plugs, respectively disposed on the substrate between the gate electrodes, in the dielectric layer. A piping defect is detected by the analysis image showing an area with voltage contrast difference.
    Type: Application
    Filed: August 30, 2005
    Publication date: June 22, 2006
    Inventors: Long-Hui Lin, Hsien-Te Lo, Chia-Yun Chen
  • Publication number: 20060050950
    Abstract: A method of managing wafer defects includes inspecting each chip in a wafer to generate a unit of wafer defect raw data, using a server to integrate the unit of wafer defect raw data to generate a unit of wafer defect distribution data for recording positions, types, and sizes of defects, using the server to generate a corresponding drawing file according to the unit wafer defect distribution data to show all kinds of defect distributions, and transmitting the drawing file to a terminal such that terminal users can view the defect distributions without receiving the unit of wafer defect raw data.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Inventors: Hung-En Tai, Chia-Yun Chen, Sheng-Jen Wang
  • Publication number: 20050248756
    Abstract: A plurality of cassettes, each having a plurality of wafers respectively having a first defect information, is selected. Each of the cassettes is then assigned to a corresponding tool having at least one reaction chamber, and the wafers are substantially equally assigned to the reaction chambers. A first process is then performed on each of the wafers in the reaction chamber. Finally, a first defect inspection process is performed on each of the wafers.
    Type: Application
    Filed: December 1, 2004
    Publication date: November 10, 2005
    Inventors: Long-Hui Lin, Chia-Yun Chen