Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: The present disclosure provides a correction system and method for correcting a semiconductor circuit. The correction system includes a plurality of redundant circuit units, a plurality of switching circuit units and a control circuit. The redundant circuit units are coupled to the semiconductor circuit. The switching circuit units are coupled to the redundant circuit units and a plurality of basic circuit units of the semiconductor circuit. The control circuit is coupled to the semiconductor circuit and the switching circuit units, is configured to obtain a noise signal of the semiconductor circuit, is configured to determine whether the semiconductor circuit passes a noise test by recognizing a characteristic of the noise signal, and is configured to replace one of the basic circuit units with one of the redundant circuit units by controlling the switching circuit units when the semiconductor circuit does not pass the noise test.

Abstract: An electronic device including a die and a connection structure electrically connected to the die is disclosed. The connection structure includes a first insulating layer including an opening, a second insulating layer, a first metal element disposed between the first insulating layer and the second insulating layer, a second metal element disposed in the opening and electrically connected to the first metal element, and a conductive element. The second metal element is electrically connected between the conductive element and the first metal element. A first surface and a second surface of the first insulating layer are contacted with the first metal element and the conductive element respectively. The first insulating layer includes first filling elements, the second insulating layer includes second filling elements, and in a cross-sectional view, a second maximum size of the second filling elements is greater than a first maximum size of the first filling elements.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: An organic electroluminescent material is used for a sensitizer layer of an organic light-emitting diode. The organic electroluminescent material includes a structure of the following General Formula (1): A is selected from the group consisting of General Formula (2), a carbazole group, and a substituted benzimidazole group. The present invention also discloses an organic light-emitting diode which has a sensitizer layer. The sensitizer layer includes a structure of General Formula (1).

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: A holding device for a top-opening substrate container includes a holding assembly for pushing a substrate actuator disposed at a substrate to operate. The holding assembly includes a holding body and a pushing actuator. The pushing actuator includes a first guiding sloped surface for pressing against a second guiding sloped surface of an inner surface of a container door structure. The first guiding sloped surface causing corresponding pushing and displacement between the first guiding sloped surface and the second guiding sloped surface according to a supporting force of the container door structure. A pushing section is connected to the first guiding sloped surface, and capable of correspondingly pushing the substrate actuator to operate according to a level of the pushing and displacement of the first guiding sloped surface, such that the substrate actuator displaces substrates and stacks the substrates with another in layers.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The height for coating of the slot die coating apparatus is adjustable, and the slurry may be exposed from the first flow path or the second flow path. Therefore, hitting the obstacle of the substrate can be avoided during coating to achieve the optimized coating.

Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The nozzle lips at the two sides of the slot die coating apparatus are extended to close the substrate to prevent to hit the obstacle of the substrate during coating. Also, the height for coating of the slot die coating apparatus is controllable to achieve the optimized coating.

Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.

Abstract: A method of synchronization of wireless communication system is provided. The method includes the following steps: receiving a symbol from a wireless communication system by a user equipment; detecting ISI-free region of the received symbol; setting an endpoint of a FFT window within the ISI-free region; detecting shifted primary control frequency and shifted secondary control frequency of the symbol; calculating ICFO based on the shifted primary control frequency and a primary control frequency; calculating secondary control frequency based on ICFO and shifted secondary control frequency; finding the preamble of a frame based on the secondary control frequency; and determining, based on the preamble, a start point of the frame.

Abstract: A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.

Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.