Patents by Inventor Chiaming Chai
Chiaming Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527274Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.Type: GrantFiled: May 27, 2021Date of Patent: December 13, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Shaoping Ge, Chiaming Chai, Jason Philip Martzloff
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Publication number: 20220383918Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Shaoping GE, Chiaming CHAI, Jason Philip MARTZLOFF
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Publication number: 20180152176Abstract: Systems and methods for pulse generation in a dual voltage domain include a first and a second voltage aware branch sensitive to a low voltage domain. The first voltage aware branch includes an inverter in the low voltage domain for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain. The second voltage aware branch includes a delay element in the low voltage domain for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Shaoping GE, Chiaming CHAI, Stephen Edward LILES, Rahul Krishnakumar NADKARNI
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Patent number: 9911472Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.Type: GrantFiled: November 28, 2016Date of Patent: March 6, 2018Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Manish Garg
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Patent number: 9608637Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.Type: GrantFiled: August 14, 2015Date of Patent: March 28, 2017Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Chintan Hemendrakumar Shah
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Publication number: 20170047930Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.Type: ApplicationFiled: August 14, 2015Publication date: February 16, 2017Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Chintan Hemendrakumar Shah
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Patent number: 9548089Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.Type: GrantFiled: June 18, 2015Date of Patent: January 17, 2017Assignee: QUALCOMM IncorporatedInventors: Stephen Edward Liles, Satendra Kumar Maurya, Kunal Garg, Chiaming Chai, Chintan Shah
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Publication number: 20160293234Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.Type: ApplicationFiled: June 18, 2015Publication date: October 6, 2016Inventors: Stephen Edward LILES, Satendra Kumar MAURYA, Kunal GARG, Chiaming CHAI, Chintan SHAH
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Patent number: 9442675Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.Type: GrantFiled: September 4, 2013Date of Patent: September 13, 2016Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles
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Patent number: 9196330Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.Type: GrantFiled: March 20, 2012Date of Patent: November 24, 2015Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Stephen E. Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Patent number: 9190141Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.Type: GrantFiled: October 28, 2013Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Satendra Kumar Maurya
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Patent number: 9007817Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.Type: GrantFiled: October 9, 2013Date of Patent: April 14, 2015Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Kunal Garg
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Publication number: 20150036418Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.Type: ApplicationFiled: October 28, 2013Publication date: February 5, 2015Applicant: QUALCOMM IncorporatedInventors: Chiaming Chai, Satendra Kumar Maurya
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Publication number: 20140337573Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.Type: ApplicationFiled: September 4, 2013Publication date: November 13, 2014Applicant: QUALCOMM IncorporatedInventors: Chiaming Chai, Shaoping Ge, Stephen E. Liles
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Publication number: 20140328113Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.Type: ApplicationFiled: October 9, 2013Publication date: November 6, 2014Applicant: QUALCOMM IncorporatedInventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Kunal Garg
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Patent number: 8638153Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.Type: GrantFiled: March 29, 2012Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Patent number: 8576612Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.Type: GrantFiled: May 6, 2011Date of Patent: November 5, 2013Assignee: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
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Publication number: 20130257498Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Publication number: 20130182514Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.Type: ApplicationFiled: March 20, 2012Publication date: July 18, 2013Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Stephen E. Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
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Patent number: 8456929Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.Type: GrantFiled: April 7, 2010Date of Patent: June 4, 2013Assignee: QUALCOMM IncorporatedInventors: Stephen Edward Liles, Chiaming Chai, Lakshmikant Mamileti