Patents by Inventor Chiaming Chai
Chiaming Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8154900Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.Type: GrantFiled: September 29, 2009Date of Patent: April 10, 2012Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael Thai Thanh Phan
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Publication number: 20110249518Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.Type: ApplicationFiled: April 7, 2010Publication date: October 13, 2011Applicant: QUALCOMM INCORPORATEDInventors: Stephen Edward Liles, Chiaming Chai, Lakshmikant Mamileti
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Publication number: 20110227639Abstract: A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Applicant: QUALCOMM IncorporatedInventors: Michael ThaiThanh Phan, Chiaming Chai, Manish Garg
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Publication number: 20110211386Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: QUALCOMM INCORPORATEDInventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
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Patent number: 8008961Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).Type: GrantFiled: December 14, 2009Date of Patent: August 30, 2011Assignee: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Jeffrey Todd Bridges
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Publication number: 20110140752Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).Type: ApplicationFiled: December 14, 2009Publication date: June 16, 2011Applicant: QUALCOMM INCORPORATEDInventors: Manish Garg, Chiaming Chai, Jeffrey Todd Bridges
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Patent number: 7961499Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.Type: GrantFiled: January 22, 2009Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
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Patent number: 7952901Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.Type: GrantFiled: August 9, 2007Date of Patent: May 31, 2011Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, David Paul Hoff, Jason Philip Martzloff, Michael ThaiThanh Phan, Manju Rathna Varma
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Patent number: 7876631Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.Type: GrantFiled: December 17, 2008Date of Patent: January 25, 2011Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Stephen Edward Liles
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Publication number: 20100182823Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Applicant: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
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Patent number: 7761774Abstract: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.Type: GrantFiled: October 28, 2005Date of Patent: July 20, 2010Assignee: QUALCOMM IncorporatedInventors: Jeffrey Herbert Fischer, Michael ThaiThanh Phan, Chiaming Chai, James Norris Dieffenderfer
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Publication number: 20100148839Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: QUALCOMM IncorporatedInventors: Chiaming Chai, Stephen Edward Liles
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Publication number: 20100023684Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.Type: ApplicationFiled: September 29, 2009Publication date: January 28, 2010Applicant: QUALCOMM INCORPORATEDInventors: CHIAMING CHAI, JEFFREY HERBERT FISCHER, MICHAEL THAI THANH PHAN
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Patent number: 7616468Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.Type: GrantFiled: August 4, 2006Date of Patent: November 10, 2009Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Patent number: 7586772Abstract: Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.Type: GrantFiled: August 4, 2006Date of Patent: September 8, 2009Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Patent number: 7564266Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.Type: GrantFiled: June 25, 2007Date of Patent: July 21, 2009Assignee: QUALCOMM IncorporatedInventors: Shaoping Ge, Chiaming Chai, Jeffrey Herbert Fischer
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Publication number: 20090040801Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.Type: ApplicationFiled: August 9, 2007Publication date: February 12, 2009Applicant: QUALCOMM INCORPORATEDInventors: Chiaming Chai, David Paul Hoff, Jason Philip Martzloff, Michael ThaiThanh Phan, Manju Rathna Varma
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Publication number: 20080315919Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Applicant: QUALCOMM INCORPORATEDInventors: Shaoping Ge, Chiaming Chai, Jeffrey Herbert Fischer
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Publication number: 20080031040Abstract: Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Inventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan
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Publication number: 20080031033Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit comprises a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Inventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael ThaiThanh Phan