Patents by Inventor Chian Liao
Chian Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11418002Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.Type: GrantFiled: October 31, 2019Date of Patent: August 16, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Yi-Chian Liao
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Publication number: 20210343546Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.Type: ApplicationFiled: June 8, 2020Publication date: November 4, 2021Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
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Patent number: 11164755Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.Type: GrantFiled: June 8, 2020Date of Patent: November 2, 2021Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
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Publication number: 20210066883Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.Type: ApplicationFiled: October 31, 2019Publication date: March 4, 2021Inventors: Kong-Toon Ng, Yi-Chian Liao
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Patent number: 9548220Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: January 4, 2016Date of Patent: January 17, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 9418874Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: GrantFiled: May 19, 2015Date of Patent: August 16, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20160118271Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 9257381Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: December 20, 2012Date of Patent: February 9, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20150255311Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: ApplicationFiled: May 19, 2015Publication date: September 10, 2015Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Patent number: 9087780Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: GrantFiled: April 29, 2013Date of Patent: July 21, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Patent number: 8829687Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.Type: GrantFiled: December 20, 2012Date of Patent: September 9, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Mu-Hsuan Chan, Wan-Ting Chen, Yi-Chian Liao, Chun-Tang Lin, Yi-Chi Lai
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Publication number: 20140084455Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.Type: ApplicationFiled: December 20, 2012Publication date: March 27, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Mu-Hsuan Chan, Wan-Ting Chen, Yi-Chian Liao, Chun-Tang Lin, Yi-Chi Lai
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Publication number: 20140077387Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: November 20, 2012Publication date: March 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi Che Lai
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Publication number: 20140070424Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: December 20, 2012Publication date: March 13, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20140027926Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: ApplicationFiled: April 29, 2013Publication date: January 30, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wang-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Patent number: 8013877Abstract: A method for rapidly generating the gray-level versus brightness curve of a display includes the step of obtaining a portion of the gray-level values and their corresponding brightness values. These values are then used in a mathematical formula to find variables to obtain the gray-level versus brightness curve.Type: GrantFiled: July 16, 2007Date of Patent: September 6, 2011Assignee: Wistron CorporationInventors: Mang Ou-Yang, Shih-Wei Huang, Jiun-Chian Liao, Gordon Horng, Tsang-Hsing Lee, Yih-Shyang Chen
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Publication number: 20110159445Abstract: Disclosed is a method for making a texture on a face of a transparent conductive film coated on a glass substrate. The method includes the steps of forming a texture on the face of the glass substrate and coating the transparent conductive film on the texture formed on the face of the glass substrate.Type: ApplicationFiled: November 18, 2010Publication date: June 30, 2011Applicant: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National DefenseInventors: Chao-Nan Wei, Hui-Yun Bor, Kuan-Zong Fung, Yi-Chian Liao
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Patent number: 7742057Abstract: A method of obtaining a new color temperature point as applied in a color display device. The color display device has a brightest temperature point when its red, green, and blue components are all in their brightest states. The method of obtaining a new color temperature point uses a mathematical method to find the new point which substantially satisfies the specific color temperature and also causes a minimum loss in brightness.Type: GrantFiled: July 16, 2007Date of Patent: June 22, 2010Assignee: Wistron CorporationInventors: Mang Ou-Yang, Shih-Wei Huang, Jiun-Chian Liao, Gordon Horng, Tsang-Hsing Lee, Yih-Shyang Chen
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Patent number: 7740393Abstract: A light guide plate (LGP) adapted to a backlight module having a light emitting surface, a bottom surface opposite to the light emitting surface, and at least one light incident surface contacting with the light emitting surface and the bottom surface is provided. The bottom surface has a plurality of flat surfaces and a plurality of groove groups. The groove groups and the flat surfaces are arranged in an alternating fashion. Each of the groove groups has at least two grooves. Each of the grooves has a first slanted surface, a peak, and a second slanted surface intersecting with the first slanted surface at the peak. In each of the grooves, a first edge side of the first slanted surface away from the peak is at a first distance from a second edge side of the second slanted surface away from the peak.Type: GrantFiled: January 28, 2008Date of Patent: June 22, 2010Assignee: Coretronic CorporationInventors: Tzeng-Ke Shiau, Ching-Shiang Li, Chao-Hung Weng, Jiun-Chian Liao, Chih-Jen Tsang
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Patent number: 7527415Abstract: A light guide plate has a bottom surface including flat surfaces (FSs) and a plurality of prism patterns (PPs) disposed alternately with the FSs, a light emitting surface (LES) and a light incident surface (LIS). Each FS is at a first distance respectively from the LES and the first distances gradually decrease along a direction away from the LIS. Each PP has a first slanted surface (FSS) and at least a groove having a second slanted surface (SSS) and a third slanted surface (TSS). The two opposite sides of the FSS are spaced out a second distance apart. The two opposite sides of the SSS are spaced out a third distance apart. The specific value of dividing a first orthogonal projection of the second distance on an axis perpendicular to the FSs by a second orthogonal projection of the third distance on the axis is between 0.5 and 1.5.Type: GrantFiled: April 2, 2008Date of Patent: May 5, 2009Assignee: Coretronic CorporationInventors: Tzeng-Ke Shiau, Chao-Hung Weng, Jiun-Chian Liao, Chih-Jen Tsang