Patents by Inventor Chian-Min Richard Ho

Chian-Min Richard Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6885983
    Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: April 26, 2005
    Assignee: Mentor Graphics Corporation
    Inventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul Il Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
  • Patent number: 6848088
    Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicated that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: January 25, 2005
    Assignee: Mentor Graphics Corporation
    Inventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
  • Publication number: 20030200515
    Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.
    Type: Application
    Filed: January 20, 2003
    Publication date: October 23, 2003
    Applicant: 0-In Design automation Inc.
    Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Ii Estrada, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Ping Fai Yeung
  • Patent number: 6609229
    Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: August 19, 2003
    Assignee: O-In Design Automation, Inc.
    Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
  • Patent number: 6292765
    Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 18, 2001
    Assignee: O-In Design Automation
    Inventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul II Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
  • Patent number: 6175946
    Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: January 16, 2001
    Assignee: O-IN Design Automation
    Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung