Abstract: A method of performing code review and a code review system are provided. The code review system includes a code repository, a static scanning tool, an analytical neural network and a generative neural network. The code repository is configured to store an original source code and a new code created by a developer in response to a code change request to merge the new code with the original source code. The static scanning tool is configured to collect data associated with each commit in the new code. The analytical neural network is implemented with an analytical AI and configured to assess a risk level of each commit in the new code. The generative neural network is implemented with a generative AI and configured to provide a code summarization and an initial code review comment of each commit in the new code.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

Abstract: A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A display device includes a display panel, a first adhesive layer, a diffusion layer, and an anti-glare film. The first adhesive layer is disposed on the display panel. The first adhesive layer is disposed between the display panel and the diffusion layer. The anti-glare film is disposed on the diffusion layer, wherein a thickness of the diffusion layer is greater than or equal to 15 microns.

Abstract: A light emitting panel includes: a substrate, a plurality of light emitting units arranged on the substrate, a diffuse reflective layer provided on the substrate and defining a plurality of openings, the light emitting units respectively positioned corresponding to the openings, and an encapsulating adhesive layer covering the light emitting units, the diffuse reflective layer and the openings on the substrate. In the light emitting panel, the vertical thickness of the encapsulating adhesive layer on the diffuse reflective layer is greater than 40 ?m.

Abstract: A semiconductor device includes a device layer with a semiconductor element, a first dielectric layer on the device layer, a first conductive line on the device layer and surrounded by the first dielectric layer, and a second dielectric layer on the first dielectric layer and around the first conductive line. The semiconductor includes a spacer disposed on the first conductive line and abutting a sidewall of the second dielectric layer, and a first conductive via disposed on the first conductive line and the spacer. The first conductive via includes a first segment positioned over the spacer and including a first width, and a second segment positioned between the first segment the first conductive line and including a second width. The first width is larger than the second width.

Abstract: Systems and methods for retinal imaging are provided. A heads-up display (HUD) can be integrated with advanced retinal imaging modalities, including optical coherence tomography (OCT) and fundoscopy (e.g., fluorescence fundoscopy). The HUD can serve as a crucial component of this approach, offering several key functionalities (e.g., a fixation target and/or a means for dark adaptation).

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate. First and second landing pads are disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and is electrically connected to the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad and the second landing pad, in which the conductive layer covers upper surfaces of the first and second landing pads and has a portion between the first landing pad and the second landing pad.

Abstract: A foldable electronic device includes a first body, a second body, a pivot and a key module. The pivot is pivotally connected between the first body and the second body. The first body and the second body is configured to rotate relatively to each other through the pivot. The key module includes a bendable substrate and a sensor embedded in the bendable substrate. The bendable substrate is connected between the first body and the second body and covers an outer side of the pivot. The sensor generates a sensing signal in response to a press of a user upon the bendable substrate.

Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives an indication of activation of Cell Discontinuous Transmission (DTX), wherein the Cell DTX is associated with one or more active periods and one or more non-active periods, and the UE is configured with a plurality of Channel State Information Reference Signal (CSI-RS) resources for deriving a CSI report. The UE determines whether to transmit the CSI report based on whether the UE receives a CSI-RS in an active period of the one or more active periods associated with the Cell DTX.

Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives an indication of an adaptation associated with Channel State Information Reference Signal (CSI-RS), wherein the adaptation is associated with switching from a first number of ports to a second number of ports, and the UE is configured with a plurality of CSI-RS resources for deriving a Channel State Information (CSI) report. The UE determines whether to transmit the CSI report based on whether the UE receives a CSI-RS associated with the second number of ports.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: A method for fabricating a semiconductor device includes the following operations. A first dielectric layer is disposed on a device layer. A second dielectric layer is disposed on the first dielectric layer. A first opening is formed in the first dielectric layer and the second dielectric layer. A conductive line is formed in the first opening, in which an upper surface of the second dielectric layer is higher than an upper surface of the conductive line. A spacer is formed on the conductive line and in a remaining portion of the first opening, in which the spacer partially covers the conductive line. A third dielectric layer is disposed on the conductive line and the second dielectric layer. A second opening is formed in the third dielectric layer. A conductive via is formed by filling the second opening with a conductive material.

Abstract: This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

Abstract: A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 ?m.

Abstract: This disclosure relates to cereblon E3 ubiquitin ligase binding compositions comprising one or more of the cereblon E3 ubiquitin ligase binding compositions, and to methods of use the cereblon E3 ubiquitin ligase binding compositions for the degrading target proteins associated with a disease or condition.

Abstract: Methods, systems, and apparatuses are provided for cancellation sequence in a wireless communication system, comprising a User Equipment (UE) being configured with or scheduled to perform a first transmission in a first resource and to perform a second transmission in a second resource, wherein the first resource overlaps with the second resource in time domain, not performing the first transmission in the first resource and performing the second transmission in the second resource if the first resource is not within a Uplink (UL) subband and the second resource is within the UL subband, and performing the first transmission in the first resource and not performing the second transmission in the second resource if the first resource is within the UL subband and the second resource is within the UL subband.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.