Patents by Inventor Chiang Lin

Chiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250240826
    Abstract: A method and device for a User Equipment (UE) are disclosed. In one embodiment, the UE determines whether to initiate a random access procedure on a cell to request SIB1 from a base station based on information related to access barring.
    Type: Application
    Filed: January 17, 2025
    Publication date: July 24, 2025
    Inventor: Ko-Chiang Lin
  • Publication number: 20250234511
    Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Inventors: YI-JEN LO, CHIANG-LIN SHIH, HSIH-YANG CHIU
  • Publication number: 20250227766
    Abstract: A method and device for a User Equipment (UE) are disclosed. In one embodiment, the UE receives an indication on a Synchronization Signal Block (SSB) with one SSB index indicating whether a first system information is provided or broadcasted or not. The UE also determines whether to initiate a random access procedure to request the first system information on a serving cell based on the indication.
    Type: Application
    Filed: January 3, 2025
    Publication date: July 10, 2025
    Inventor: Ko-Chiang Lin
  • Publication number: 20250227767
    Abstract: A method and device for a User Equipment (UE) are disclosed. In one embodiment, the UE initiates a random access procedure to request a first system information on a serving cell. Furthermore, the UE receives an indication in a Random Access Response (RAR) indicating a time pattern and/or periodicity and/or offset and/or search space for monitoring a Physical Downlink Control Channel (PDCCH) for the first system information. In addition, the UE monitors the PDCCH for the first system information on the serving cell based on the indication in the RAR.
    Type: Application
    Filed: January 3, 2025
    Publication date: July 10, 2025
    Inventor: Ko-Chiang Lin
  • Patent number: 12341007
    Abstract: A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: June 24, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yun-An Chen, Hsiao-Shan Huang, Hsiao-Chiang Lin
  • Publication number: 20250197409
    Abstract: Provided is a bifunctional compound, or a pharmaceutically acceptable salt, hydrate, solvate, metabolite or prodrug thereof, wherein the bifunctional compound is represented by Formula (I): ABM-L-CLM??(I); wherein: ABM is an androgen receptor binding moiety; -L- is a linking moiety; and CLM is a cereblon E3 ubiquitin ligase binding moiety represented by Formula (II)-1: wherein one end of the -L- is covalently joined to Q3, Q4, Q5 or Q6; and the other end of the -L- is covalently joined to the ABM. Also provided are a pharmaceutical composition comprising the bifunctional compound and a method for treating an androgen receptor related disease or disorder by administering the bifunctional compound.
    Type: Application
    Filed: June 29, 2023
    Publication date: June 19, 2025
    Inventors: Chu-Chiang Lin, Hung-Chuan Chen, Pei-Chin Cheng, Chih-Chang Chou
  • Publication number: 20250147863
    Abstract: A method of performing code review and a code review system are provided. The code review system includes a code repository, a static scanning tool, an analytical neural network and a generative neural network. The code repository is configured to store an original source code and a new code created by a developer in response to a code change request to merge the new code with the original source code. The static scanning tool is configured to collect data associated with each commit in the new code. The analytical neural network is implemented with an analytical AI and configured to assess a risk level of each commit in the new code. The generative neural network is implemented with a generative AI and configured to provide a code summarization and an initial code review comment of each commit in the new code.
    Type: Application
    Filed: November 4, 2024
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Min-Shan Huang, Hui-Chi Kuo, Wei-Geng Fan, Chin-Tang Lai, Chiang-Lin Lu, Chia-Shun Yeh
  • Patent number: 12295137
    Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: May 6, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Chiang-Lin Shih, Hsih-Yang Chiu
  • Patent number: 12284447
    Abstract: A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Chang-Chiang Lin
  • Patent number: 12278211
    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: April 15, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
  • Publication number: 20250116798
    Abstract: A display device includes a display panel, a first adhesive layer, a diffusion layer, and an anti-glare film. The first adhesive layer is disposed on the display panel. The first adhesive layer is disposed between the display panel and the diffusion layer. The anti-glare film is disposed on the diffusion layer, wherein a thickness of the diffusion layer is greater than or equal to 15 microns.
    Type: Application
    Filed: August 26, 2024
    Publication date: April 10, 2025
    Applicant: AUO Corporation
    Inventors: Hao Shiun Yang, Jian-Fu Chen, Chien-Chi Chen, Shang-Chiang Lin, Wang-Shuo Kao
  • Publication number: 20250118712
    Abstract: A light emitting panel includes: a substrate, a plurality of light emitting units arranged on the substrate, a diffuse reflective layer provided on the substrate and defining a plurality of openings, the light emitting units respectively positioned corresponding to the openings, and an encapsulating adhesive layer covering the light emitting units, the diffuse reflective layer and the openings on the substrate. In the light emitting panel, the vertical thickness of the encapsulating adhesive layer on the diffuse reflective layer is greater than 40 ?m.
    Type: Application
    Filed: July 5, 2024
    Publication date: April 10, 2025
    Inventors: JHONG-YUAN WANG, SHANG-CHIANG LIN, YA-LING HSU
  • Patent number: 12262947
    Abstract: Systems and methods for retinal imaging are provided. A heads-up display (HUD) can be integrated with advanced retinal imaging modalities, including optical coherence tomography (OCT) and fundoscopy (e.g., fluorescence fundoscopy). The HUD can serve as a crucial component of this approach, offering several key functionalities (e.g., a fixation target and/or a means for dark adaptation).
    Type: Grant
    Filed: September 30, 2024
    Date of Patent: April 1, 2025
    Assignee: The Florida International University Board of Trustees
    Inventors: Wei-Chiang Lin, Shuliang Jiao, Rui Zhou, Nikolaos Tsoukias
  • Patent number: 12266564
    Abstract: A semiconductor device includes a device layer with a semiconductor element, a first dielectric layer on the device layer, a first conductive line on the device layer and surrounded by the first dielectric layer, and a second dielectric layer on the first dielectric layer and around the first conductive line. The semiconductor includes a spacer disposed on the first conductive line and abutting a sidewall of the second dielectric layer, and a first conductive via disposed on the first conductive line and the spacer. The first conductive via includes a first segment positioned over the spacer and including a first width, and a second segment positioned between the first segment the first conductive line and including a second width. The first width is larger than the second width.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 1, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Publication number: 20250096048
    Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate. First and second landing pads are disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and is electrically connected to the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad and the second landing pad, in which the conductive layer covers upper surfaces of the first and second landing pads and has a portion between the first landing pad and the second landing pad.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Inventors: Chiang-Lin SHIH, Hsueh-Han LU, Yu-Ting LIN
  • Patent number: 12228969
    Abstract: A foldable electronic device includes a first body, a second body, a pivot and a key module. The pivot is pivotally connected between the first body and the second body. The first body and the second body is configured to rotate relatively to each other through the pivot. The key module includes a bendable substrate and a sensor embedded in the bendable substrate. The bendable substrate is connected between the first body and the second body and covers an outer side of the pivot. The sensor generates a sensing signal in response to a press of a user upon the bendable substrate.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 18, 2025
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Te-Wei Huang, Pei-Chiang Lin, Sih-Ci Li
  • Publication number: 20250038919
    Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives an indication of an adaptation associated with Channel State Information Reference Signal (CSI-RS), wherein the adaptation is associated with switching from a first number of ports to a second number of ports, and the UE is configured with a plurality of CSI-RS resources for deriving a Channel State Information (CSI) report. The UE determines whether to transmit the CSI report based on whether the UE receives a CSI-RS associated with the second number of ports.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventor: Ko-Chiang Lin
  • Publication number: 20250038812
    Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives an indication of activation of Cell Discontinuous Transmission (DTX), wherein the Cell DTX is associated with one or more active periods and one or more non-active periods, and the UE is configured with a plurality of Channel State Information Reference Signal (CSI-RS) resources for deriving a CSI report. The UE determines whether to transmit the CSI report based on whether the UE receives a CSI-RS in an active period of the one or more active periods associated with the Cell DTX.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventor: Ko-Chiang Lin
  • Patent number: 12198991
    Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 14, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin
  • Publication number: 20250006551
    Abstract: A method for fabricating a semiconductor device includes the following operations. A first dielectric layer is disposed on a device layer. A second dielectric layer is disposed on the first dielectric layer. A first opening is formed in the first dielectric layer and the second dielectric layer. A conductive line is formed in the first opening, in which an upper surface of the second dielectric layer is higher than an upper surface of the conductive line. A spacer is formed on the conductive line and in a remaining portion of the first opening, in which the spacer partially covers the conductive line. A third dielectric layer is disposed on the conductive line and the second dielectric layer. A second opening is formed in the third dielectric layer. A conductive via is formed by filling the second opening with a conductive material.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 2, 2025
    Inventors: Chiang-Lin SHIH, Shing-Yih SHIH