Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.

Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof.

Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: An image sensor includes a photodiode within a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL), a plurality of dielectric layers over the CESL and a plurality of metallization layers in the plurality of dielectric layers. At least one dielectric layer of the plurality of dielectric layers includes a low-k dielectric material. An opening is extended through the plurality of dielectric layers to expose a portion of the CESL above an active region of the photodiode. A cap layer is on sidewalls of the opening. The cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: An image sensor includes a photodiode within a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL), a plurality of dielectric layers over the CESL and a plurality of metallization layers in the plurality of dielectric layers. At least one dielectric layer of the plurality of dielectric layers includes a low-k dielectric material. An opening is extended through the plurality of dielectric layers to expose a portion of the CESL above an active region of the photodiode. A cap layer is on sidewalls of the opening. The cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.

Abstract: A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.

Abstract: A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.