Abstract: Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.

Abstract: A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device coupled in parallel between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A semiconductor structure includes a silicon carbide layer, which has a unit region and a termination region surrounding the unit region. A first guard ring structure is located in the termination region of the silicon carbide layer, and adjoins a top surface of the silicon carbide layer. The first guard ring structure may include at least one first guard ring well region. A second guard ring structure is located in the silicon carbide layer and below the first guard ring structure. The second guard ring structure may include at least one second guard ring well region, which corresponds to the at least one first guard ring well region in a vertical direction. A method for manufacturing the semiconductor structure is also provided.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device connected in series between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to each other, and a unit region and a terminal region adjacent to each other. An electrode structure in the substrate extends from the first surface toward the second surface in the unit region. A trench structure in the substrate extends from the first surface toward the second surface in the unit region and adjoins the terminal region. The trench structure includes a semiconductor material layer extending to the first surface. A capacitive structure on the first surface of the substrate in the terminal region adjoins the trench structure. The capacitive structure has a material the same as the semiconductor material layer, and has a capacitive electrode connected to the semiconductor material layer. A method for manufacturing the semiconductor structure is also provided.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A vertical power semiconductor device includes a semiconductor material layer having a first surface and a second surface opposite each other. A first electrode structure and a second electrode structure are arranged in the semiconductor material layer, extending from the first surface to the second surface. A first doped region having a first conductivity type is arranged between the first and second electrode structures. A second doped region having a second conductivity type is in the first doped region. The second doped region is close to the bottom of the first doped region and separated from the first surface. A third doped region having the second conductivity type is between the bottom of the first doped region and the second surface. A conductive plug is between the first and second electrode structures and separated from the third doped region. A method for manufacturing the semiconductor device is also provided.

Abstract: A vertical semiconductor power device is provided, which includes a substrate having a first surface and a second surface opposite to each other. A trench extends from the second surface toward the first surface. An in-trench dielectric layer is disposed along an inner surface of the trench. A shield electrode is disposed in the trench and is surrounded by the in-trench dielectric layer. A gate electrode is disposed in the in-trench dielectric layer and surrounds the shield electrode. The gate electrode is surrounded by the in-trench dielectric layer without adjoining the shield electrode and the substrate. A method for making the vertical semiconductor power device is also provided.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.

Abstract: A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.