Patents by Inventor Chiao-Shun Chuang

Chiao-Shun Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030060033
    Abstract: Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate.
    Type: Application
    Filed: August 13, 2002
    Publication date: March 27, 2003
    Applicant: MOSEL VITELIC, INC. A Taiwanese Corporation
    Inventors: Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng, Hsin-Huang Hsieh
  • Publication number: 20020006704
    Abstract: A process for forming a gate oxide layer of a trench power MOSFET is provided. The process includes steps of providing a silicon substrate, forming a mask layer on the silicon substrate, removing a portion of the mask layer to expose a portion of the silicon substrate, removing the exposed portion of the silicon substrate to form the trench, removing remaining portion of the mask layer, forming a sacrificial oxide layer on the silicon substrate and on the bottom and sidewall of the trench by thermal oxidation under an operating temperature ranged from 1150 to 1300° C. and an operating time ranged from 20 to 60 minutes, removing the sacrificial oxide layer, and forming a gate oxide layer on the silicon substrate and on the bottom and sidewall of the trench.
    Type: Application
    Filed: January 12, 2001
    Publication date: January 17, 2002
    Applicant: Mosel Vitelic Inc.
    Inventors: Mao-Song Tseng, Su-Wen Chang, Chien-Ping Chang, Chiao-Shun Chuang