Patents by Inventor Chiao-Wen Yeh
Chiao-Wen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230284463Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a memory element, a spacer structure, and an upper element structure. The memory element includes a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.Type: ApplicationFiled: March 4, 2022Publication date: September 7, 2023Inventors: Erh-Kun LAI, Hsiang-Lan LUNG, Chiao-Wen YEH
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Publication number: 20220069211Abstract: A pillar-shaped structure and a line-shaped structure are described that include a supporting top conductive layer, an active material layer, such as a memory material or switching material, and a bottom conductive layer. The active material layer is more narrow than the supporting top conductive layer. A supporting side insulating layer is formed connecting the top and bottom conductive layers to provide structure stability. A void, or air gap, is formed between the active material layer and the supporting side insulating layer, which can provide improved thermal isolation between adjacent pillar-shaped or line-shaped structures.Type: ApplicationFiled: September 3, 2020Publication date: March 3, 2022Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsiang-Lan LUNG, Chiao-Wen YEH
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Patent number: 10950786Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.Type: GrantFiled: January 28, 2019Date of Patent: March 16, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Chiao-Wen Yeh
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Patent number: 10818729Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.Type: GrantFiled: December 27, 2018Date of Patent: October 27, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Ming-Hsiu Lee, Chiao-Wen Yeh
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Publication number: 20190355903Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.Type: ApplicationFiled: January 28, 2019Publication date: November 21, 2019Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsiang-Lan LUNG, Erh-Kun LAI, Chiao-Wen YEH
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Publication number: 20190355790Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.Type: ApplicationFiled: December 27, 2018Publication date: November 21, 2019Inventors: Hsiang-Lan LUNG, Erh-Kun LAI, Ming-Hsiu LEE, Chiao-Wen YEH
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Patent number: 9882126Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.Type: GrantFiled: April 9, 2016Date of Patent: January 30, 2018Assignees: International Business Machines Corporation, Macronix International Co. LtdInventors: Matthew J. BrightSky, Huai-Yu Cheng, Wei-Chih Chien, Sangbum Kim, Chiao-Wen Yeh
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Publication number: 20170294578Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.Type: ApplicationFiled: April 9, 2016Publication date: October 12, 2017Applicants: International Business Machines Corporation, Macronix International Co., LtdInventors: Matthew J. BrightSky, Huai-Yu Cheng, Wei-Chih Chien, Sangbum Kim, Chiao-Wen Yeh
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Patent number: 9780264Abstract: The present application discloses a light-emitting element comprising a semiconductor light-emitting stack emitting a first light which has a first color coordinate, a first wavelength conversion material on the semiconductor light-emitting stack converting the first light to emit a second light, and a second wavelength conversion material on the first wavelength conversion material converting the second light to emit a third light. The first light and the second light are mixed to be a fourth light having a second color coordinate. The third light and the fourth light are mixed to be a fifth light having a third color coordinate, and the second color coordinate locates at the top right of the first color coordinate and the third color coordinate locates at the top right of the second color coordinate.Type: GrantFiled: July 24, 2014Date of Patent: October 3, 2017Assignee: EPISTAR CORPORATIONInventors: Chiao-Wen Yeh, Hsing-Chao Chen, Pei-Lun Chien
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Patent number: 9765258Abstract: Provided is a metal oxonitridosilicate phosphor of a general formula M5?z?a?bAl3+xSi23?xN37?x?2aOx+2a:Euz,Mnb, wherein M is one or more alkaline earth metals; 0; 0; 0<z?; and 0<b?.Type: GrantFiled: October 18, 2013Date of Patent: September 19, 2017Assignee: EPISTAR CORPORATIONInventors: Chiao-Wen Yeh, Ru-Shi Liu
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Publication number: 20150028374Abstract: The present application discloses a light-emitting element comprising a semiconductor light-emitting stack emitting a first light which has a first color coordinate, a first wavelength conversion material on the semiconductor light-emitting stack converting the first light to emit a second light, and a second wavelength conversion material on the first wavelength conversion material converting the second light to emit a third light. The first light and the second light are mixed to be a fourth light having a second color coordinate. The third light and the fourth light are mixed to be a fifth light having a third color coordinate, and the second color coordinate locates at the top right of the first color coordinate and the third color coordinate locates at the top right of the second color coordinate.Type: ApplicationFiled: July 24, 2014Publication date: January 29, 2015Inventors: Chiao-Wen YEH, Hsing-Chao CHEN, Pei-Lun Chien
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Patent number: 8716731Abstract: The present disclosure provides an illuminating system including a light emitting diode (LED); and a tunable luminescent material disposed approximate the light-emitting diode, wherein the tunable luminescent material includes alkaline earth metal (AE) and silicon aluminum nitride doped by a rare earth element (RE), formulated as (AE)Si6?pAlpN8, wherein p is a parameter defining a relative aluminum content in weight and p is greater than zero.Type: GrantFiled: April 11, 2011Date of Patent: May 6, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Chiao-Wen Yeh, Ru-Shi Liu
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Publication number: 20140110632Abstract: Provided is a metal oxonitridosilicate phosphor of a general formula M5?z?a?bAl3+xSi23?xN37?x?2aOx+2a: Euz, Mnb, wherein M is one or more alkaline earth metals; 0?x?7; 0?a?1; 0<z?0.3; and 0<b?0.3.Type: ApplicationFiled: October 18, 2013Publication date: April 24, 2014Applicant: EPISTAR CORPORATIONInventors: Chiao-Wen YEH, Ru-Shi LIU
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Patent number: 8585929Abstract: Disclosed is a phosphor and a method for preparing the same. The phosphor comprises a material having a general composition formula expressed by M1Si6N8-XOX (satisfying 0?x?1), where M is alkaline earth metal.Type: GrantFiled: September 23, 2011Date of Patent: November 19, 2013Assignee: Epistar CorporationInventors: Chiao-Wen Yeh, Ru-Shi Liu
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Publication number: 20130075660Abstract: Disclosed is a phosphor and a method for preparing the same. The phosphor comprises a material having a general composition formula expressed by M1Si6N8?xOx (satisfying 0?x?1), where M is alkaline earth metal.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Epistar CorporationInventors: Chiao-Wen YEH, Ru-Shi Liu
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Patent number: 8343785Abstract: The present disclosure provides a radiation device. The radiation device includes a first light emitting diode (LED) operable to emit light having a first central wavelength; a second LED configured adjacent the first LED and operable to emit light having a second central wavelength substantially less than the first central wavelength; and a luminescent material disposed on the first LED and the second LED. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium, lithium (Ce3+, Li+).Type: GrantFiled: November 30, 2010Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiao-Wen Yeh, Ru-Shi Liu
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Patent number: 8329484Abstract: The present disclosure provides an illuminating system including a light emitting device and a luminescent material disposed approximate the light-emitting device. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium (Ce3+) and lithium (Li+).Type: GrantFiled: November 2, 2010Date of Patent: December 11, 2012Assignee: TSMC Solid State Lighting Ltd.Inventors: Chiao-Wen Yeh, Ru-Shi Liu
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Patent number: 8324743Abstract: A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate.Type: GrantFiled: June 11, 2010Date of Patent: December 4, 2012Assignee: Macronix International Co., Ltd.Inventors: Chiao-Wen Yeh, Chih-Hao Huang
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Publication number: 20120256212Abstract: The present disclosure provides an illuminating system including a light emitting diode (LED); and a tunable luminescent material disposed approximate the light-emitting diode, wherein the tunable luminescent material includes alkaline earth metal (AE) and silicon aluminum nitride doped by a rare earth element (RE), formulated as (AE)Si6?pAlpN8, wherein p is a parameter defining a relative aluminum content in weight and p is greater than zero.Type: ApplicationFiled: April 11, 2011Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiao-Wen Yeh, Ru-Shi Liu
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Publication number: 20120132936Abstract: The present disclosure provides a radiation device. The radiation device includes a first light emitting diode (LED) operable to emit light having a first central wavelength; a second LED configured adjacent the first LED and operable to emit light having a second central wavelength substantially less than the first central wavelength; and a luminescent material disposed on the first LED and the second LED. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium, lithium (Ce3+, Li+).Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiao-Wen Yeh, Ru-Shi Liu