Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.

Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.

Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area.

Abstract: A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.