Patents by Inventor Chieh-An CHANG

Chieh-An CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240045209
    Abstract: A method, includes providing a wafer including a first surface grating extending over a first area of a surface of the wafer and a second surface grating extending over a second area of the surface of the wafer; de-functionalizing a portion of the surface grating in at least one of the first surface grating area and the second surface grating area; and singulating an eyepiece from the wafer, the eyepiece including a portion of the first surface grating area and a portion of the second surface grating area. The first surface grating in the eyepiece corresponds to an input coupling grating for a head-mounted display and the second surface grating corresponds to a pupil expander grating for the head-mounted display.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 8, 2024
    Inventors: Chieh Chang, Christophe Peroz, Ryan Jason Ong, Ling Li, Sharad D. Bhagat, Samarth Bhargava
  • Publication number: 20240047403
    Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Chieh CHANG, Po-Hao TSAI, Ming-Da CHENG, Wen-Hsiung LU, Hsu-Lun LIU
  • Publication number: 20240038978
    Abstract: The present invention provides a titanium-niobium composite oxide, which includes titanium, niobium, dopant M and oxygen, and the molar ratio of the titanium, niobium and dopant M is 1:(2?x):x, and x is 0.01 to 0.2; wherein the dopant M is doped in a crystal structure with a monoclinic crystal structure formed from the titanium, niobium and oxygen, and the dopant M is at least one metal element selected from the group consisting of Sn, Al and Zr. The present invention further provides a preparation method of the titanium-niobium composite oxide, an active material and a lithium ion secondary battery using the same. The titanium-niobium composite oxide produced by the present invention has better electrical performance than the existing negative electrode materials, so that the lithium ion secondary battery using it can exhibit longer cycle life, larger electric capacity and faster charging and discharging performance, thereby having a bright prospect of the application.
    Type: Application
    Filed: February 6, 2023
    Publication date: February 1, 2024
    Applicant: GUS TECHNOLOGY CO., LTD.
    Inventors: Chung-Chieh CHANG, Kuo-Wei YEH, Wen-Chia HSU, Jia-Hui WANG, Chia-Huan CHUNG, Dong-Ze WU, PREM CHANDAN DEVANGA
  • Publication number: 20240036321
    Abstract: In some embodiments, a near-eye, near-eye display system comprises a stack of waveguides having pillars in a central, active portion of the waveguides. The active portion may include light outcoupling optical elements configured to outcouple image light from the waveguides towards the eye of a viewer. The pillars extend between and separate neighboring ones of the waveguides. The light outcoupling optical elements may include diffractive optical elements that are formed simultaneously with the pillars, for example, by imprinting or casting. The pillars are disposed on one or more major surfaces of each of the waveguides. The pillars may define a distance between two adjacent waveguides of the stack of waveguides. The pillars may be bonded to adjacent waveguides may be using one or more of the systems, methods, or devices herein. The bonding provides a high level of thermal stability to the waveguide stack, to resist deformation as temperatures change.
    Type: Application
    Filed: December 21, 2021
    Publication date: February 1, 2024
    Inventors: Ling Li, Christophe Peroz, Chieh Chang, Sharad D. Bhagat, Ryan Jason Ong, Ali Karbasi, Stephen Richard Rugg, Mauro Melli, Kevin Messer, Brian George Hill, Melanie Maputol West
  • Patent number: 11884497
    Abstract: A method of picking a top component reel from a stack of component reels includes lowering a picking arm over a rod extending through the stack of component reels to above a top component reel of the stack, the arm comprising a plurality of alignment tabs and a gripper positioned such that, with the picking arm lowered the rod extends through the gripper and between the alignment tabs of the picking arm. The method includes actuating the alignment tabs to engage the rod and align the rod with respect to the picking arm, inserting a portion of the gripper into a hole of the top component reel, actuating the gripper to engage opposing inner surfaces of the top component reel at the hole of the top component reel, and with the gripper engaged, raising the picking arm to lift the top component reel from the stack of component reels.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 30, 2024
    Assignees: Accu-Assembly Incorporated, Ascentex Industry Corporation
    Inventors: Yuen-Foo Michael Kou, Min Chieh Chang
  • Patent number: 11886000
    Abstract: In some embodiments, a head-mounted, near-eye display system comprises a stack of waveguides having integral spacers separating the waveguides. The waveguides may each include diffractive optical elements that are formed simultaneously with the spacers by imprinting. The spacers are disposed on one major surface of each of the waveguides and indentations are provided on an opposite major surface of each of the waveguides. The indentations are sized and positioned to align with the spacers, thereby forming a self-aligned stack of waveguides. Tops of the spacers may be provided with light scattering features, anti-reflective coatings, and/or light absorbing adhesive to prevent light leakage between the waveguides. As seen in a top-down view, the spacers may be elongated along the same axis as the diffractive optical elements. The waveguides may include structures (e.g.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: January 30, 2024
    Assignee: Magic Leap, Inc.
    Inventors: Christophe Peroz, Chieh Chang, Sharad D. Bhagat, Victor Kai Liu, Roy Matthew Patterson, David Carl Jurbergs, Mohammadreza Khorasaninejad, Ling Li, Michael Nevin Miller, Charles Scott Carden
  • Publication number: 20240019789
    Abstract: A reticle is pre-heated prior to an exposure operation of a semiconductor substrate lot to reduce substrate to substrate temperature variations of the reticle in the exposure operation. The reticle may be pre-heated while being stored in a reticle storage slot, while being transferred from the reticle storage slot to a reticle stage of an exposure tool, and/or in another location prior to being secured to the reticle stage for the exposure operation. In this way, the reduction in temperature variation of the reticle in the exposure operation provided by pre-heating the reticle may reduce overlay deltas and misalignment for the semiconductor substrates that are processed in the exposure operation. This increases overlay performance, increases yield of the exposure tool, and increases semiconductor device quality.
    Type: Application
    Filed: August 9, 2023
    Publication date: January 18, 2024
    Inventors: Kai-Chieh CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20240014321
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 11, 2024
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 11868112
    Abstract: A multi-point measurement system and a multi-point measurement method are provided. The multi-point measurement system is for measuring a device under testing and comprises a plurality of sensors and a computing device. The sensors are respectively attached to a plurality of measuring points of the device under testing. The computing device comprises a computing unit and a storage unit; the computing unit comprises a learning module, and the computing device establishes communication connections to the sensors respectively. The sensors generate original sensing data and transmit them to the storage unit for storage. The computing unit inputs processed sensing data obtained by preprocessing the original sensing data into the learning module for data analysis, and obtains a plurality of reference values corresponding to the sensors respectively.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: January 9, 2024
    Assignee: SMART TAG INC.
    Inventor: Kun-Chieh Chang
  • Patent number: 11867969
    Abstract: An optical element driving mechanism has an optical axis and includes a fixed portion, a movable portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The driving assembly moves in a first direction to move the movable portion in a second direction, wherein the first direction is different from the second direction.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Jungsuck Ryoo, Chieh-An Chang, Min-Hsiu Tsai, Chao-Chang Hu, Shu-Shan Chen, Pai-Jui Cheng, Chao-Hsi Wang
  • Publication number: 20240006575
    Abstract: A light emitting device including a substrate, a first pad, a second pad, a light emitting diode, a first connection structure, a second connection structure, and a patterned adhesive layer and a method for manufacturing the same are provided. The first pad and the second pad are located on the substrate. The light emitting diode includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, a first electrode and a second electrode. The first electrode and the second electrode are respectively connected to the first semiconductor layer and the second semiconductor layer. The first connection structure electrically connects the first electrode to the first pad. The second connection structure electrically connects the second electrode to the second pad. The patterned adhesive layer is located between the substrate and the light emitting diode and does not contact the first connection structure and the second connection structure.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 4, 2024
    Applicant: AUO Corporation
    Inventors: Fang-Cheng Yu, Cheng-Chieh Chang, Cheng-Yeh Tsai
  • Publication number: 20240008171
    Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.
    Type: Application
    Filed: May 4, 2023
    Publication date: January 4, 2024
    Inventors: Wei-Teng Lin, Hui-Yu Huang, Ching-Chi Chan, Shih-Chieh Chang
  • Patent number: 11854872
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11855176
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 11850704
    Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Yen-Ting Chen, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11854811
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Publication number: 20230405036
    Abstract: Disclosed herein is a UV mutagenesis produced new Streptomyces spororaveus strain SC263 that exhibits an increased thermostability of the antibiotic produced, which shows antibiotic activity against bacteria and fungi. Also provided are the antibiotic produced by SC263 and a composition thereof for treatment of bacterial and fungal infections. The antibiotic has a very high molecular weight, which is suitable for topical administration.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 21, 2023
    Applicant: National Taipei University of Technology
    Inventors: Chih-Hung Huang, Pu-Chieh Chang
  • Patent number: D1014773
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1014774
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng, Chuan-Hsi Chang
  • Patent number: D1014775
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng