Abstract: A display apparatus adapted for connecting with a supporting stand is provided. The supporting stand includes a clamping portion. The display apparatus includes a main body. The main body includes a back surface. The back surface includes a connecting hole. A fixing component is in the connecting hole. The clamping portion is adapted to reach into the connecting hole. When the clamping portion reaches into the connecting hole, the clamping portion is arranged around and abuts against the fixing component, so that the display apparatus is connected to the supporting stand.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite to the first side; a first optical element at the first side of the substrate; and a semiconductor stack on the substrate. The semiconductor stack includes a first reflective structure; a second reflective structure; a cavity region between the first reflective structure and the second reflective structure and having a first surface and a second surface opposite to the first surface; and a confinement layer in one of the second reflective structure and the first reflective structure. The semiconductor device further includes a first electrode and a second electrode on the first surface.

Abstract: In some embodiments, the present disclosure relates to a single-photon avalanche detector (SPAD) device including a silicon substrate including a recess in an upper surface of the silicon substrate. A p-type region is arranged in the silicon substrate below a lower surface of the recess. An n-type avalanche region is arranged in the silicon substrate below the p-type region and meets the p-type region at a p-n junction. A germanium region is disposed within the recess over the p-n junction.

Abstract: A computing system initialization system includes a BIOS processing system coupled to a computing device via a first I/O access connection, to a BIOS memory system via a second I/O access connection that is a relatively higher speed I/O access connection than the first I/O connection, and to a BIOS module. The BIOS processing system retrieves device data from the computing device via the first I/O access connection, stores the device data in the BIOS memory system via the second I/O access connection, and performs initialization operations subsequent to storing the device data in the BIOS memory system. During the initialization operations, the BIOS processing determines that the BIOS module requires the device data and, in response, retrieves the device data from the BIOS memory system via the second I/O access connection, and provides the device data that was retrieved from the BIOS memory system to the BIOS module.

Abstract: A vehicle platoon following deciding system based on cloud computing is configured to decide a plurality of vehicle platoon accelerations of a leading vehicle and at least one following vehicle. A cloud processing unit receives a leading vehicle parameter group and at least one following vehicle parameter group. The cloud processing unit is configured to implement a cloud deciding step. The cloud deciding step includes judging whether the leading vehicle is manually driven according to the leading vehicle parameter group to generate a driving mode judging result, calculating a driving acceleration range according to a leading vehicle acceleration range and at least one following vehicle acceleration range, estimating a compensated acceleration according to the leading vehicle parameter group, and calculating the vehicle platoon accelerations according to the driving mode judging result and at least one of the driving acceleration range and the compensated acceleration.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: A system for generating algorithmic models comprising a function module to generate a desirability function, an automated machine learning module, and a UI module. The desirability function defines a single desirability value based on an algorithmic model accuracy criteria, criteria for algorithmic model quality, criteria for model fidelity, and criteria for the benefits and cost of model deployment. Specific hard and soft constraints regarding these and other user-defined criteria can also be specified by the user. The automated machine learning module generates an algorithmic model by training the algorithmic model against a model data set, identifying the model with the greatest desirability with respect to all criteria as combined via the desirability function. The UI module generates a user interface to display the overall desirability as well as all model criteria configured by the user. The displayed criteria and desirability are selectable and definable.

Abstract: A semiconductor light emitting device includes a substrate, a first epitaxial structure and a second epitaxial structure, a connecting layer, a first electrode structure, a second electrode structure, and a third electrode structure. The first epitaxial structure and the second epitaxial structure are on the substrate side by side. The connecting layer is between the first epitaxial structure and the substrate, between the second epitaxial structure and the substrate, and between the first epitaxial structure and the second epitaxial structure. The first electrode structure is on the first epitaxial structure away from the substrate. The second electrode structure is on the second epitaxial structure away from the substrate. The third electrode structure is connected to the connecting layer.

Abstract: A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Abstract: A cross laser calibration device used to calibrate a tool center point is provided. The calibration device includes a coordinate orifice plate, a set of cross laser sensors and a rotational and translational movement mechanism. The coordinate orifice plate has an orifice center point. The set of cross laser sensors is arranged on the coordinate orifice plate to generate cross laser lines intersecting at the orifice center point. The set of cross laser sensors is driven by the second motor to rotate around the center point of the second motor, wherein the orifice center point has an off-axis setting relative to the center point of the second motor.

Abstract: A locking mechanism is provided. The locking mechanism includes a base, a connecting rod, a fastener, and a linking member. The connecting rod and the fastener penetrate the base and are rotatable relative to the base. The connecting rod and the fastener are disposed parallel to each other. The linking member is connected to the connecting rod and the fastener, and is configured to link up the connecting rod and the fastener. Accordingly, the locking mechanism may be suitable for an expansion device with a specific size, and therefore the performance and the design flexibility of the electronic apparatus may be enhanced.

Abstract: This disclosure provides a method of protecting a subject for exercise that prevents an exercise-related harmful effect and reducing exercise fatigue in the subject to thereby enhance physical performance and promote anti-fatigue and anti-inflammatory effects in the subject.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.

Abstract: A driving risk assessment and control decision-making method for an autonomous vehicle includes: detecting the surrounding state of the vehicle multiple times to generate multiple sensing signals; quantifying the sensing signals to generate multiple sensing values and calculating a sensing average value of the sensing values; calculating a sensing error value between each sensing value and the sensing average value, a sensing error average value of sensing error values and a sensing error variation value; integrating the sensing error average value, the sensing error variation value and a sensor systematic error average value and a sensor systematic error variation value to generate a sensing signal correction value; combining the sensing values and the sensing signal correction value to generate multiple sensing signal reference values; judging whether a stability of the sensing signal reference values falls within a preset range; generating a control mechanism based on the judgement.

Abstract: Disclosed herein are methods and compositions for reducing and/or preventing hair greying in a subject.

Abstract: A biofuel cell includes a cathode, an anode, and a microbial community. At least one of the anode and the cathode contains a biochar prepared from a Trapa natans husk as an electrode material, and the anode is located in the microbial community. By using the biochar prepared from the Trapa natans husk as the electrode material, not only can the power density of the biofuel cell be increased, but the economic benefits of waste recycling can also be achieved.

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.