Patents by Inventor Chieh LI

Chieh LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063866
    Abstract: A display apparatus includes a driving backplane, a plurality of light emitting components, a first bank layer and a plurality of scattering particles. The first bank layer is disposed on the driving backplane. The first bank layer has a plurality of first openings and a plurality of oblique surfaces defining the first openings. The light emitting components respectively overlap with the first openings of the first bank layer. The scattering particles are disposed on a plurality of light emitting surfaces of the light emitting components. A plurality of air gaps exist between the scattering particles and the oblique surfaces of the first bank layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 20, 2025
    Inventors: Chun-Chieh Li, Sheng-Ming Huang, Han-Sheng Nian, Yu-Cheng Shih, Hsin-Hung Li
  • Publication number: 20250031735
    Abstract: A wine tasting carrier corresponding to a selected wine is disclosed. The wine tasting carrier includes: an original carrier being in a shape of human's tongue; a flavourless region arranged on the original carrier; a flavor carrying region arranged on the original carrier and providing a flavor; a producing material attached on the flavor carrying region to provide the flavor of the flavor carrying region; and a boundary line arranged on the original carrier to separate the flavor carrying region and the flavourless region. The flavor carrying region is arranged at a tip position, a middle position, a rear position, a circular area from a front to two sides, or two separated sides of the wine tasting carrier, and the flavor of the flavor carrying region is corresponding to one flavor or aroma of the selected wine according to the arranged position of the flavor carrying region.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 30, 2025
    Inventor: Chieh-Li HSU
  • Publication number: 20250007655
    Abstract: An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, MIN-SHUEH YUAN
  • Patent number: 12180062
    Abstract: A microelectromechanical apparatus includes a base and a thin film including a stationary part disposed on the base, a peripheral part, a central part surrounded by the peripheral part, and a first and second elastic part. The first elastic part is connected to the stationary part and the peripheral part. The second elastic part is connected to the peripheral part and the central part. When low frequency signal is input to a first electrode of the first elastic part, the peripheral part and the and the central part respectively vibrate with a first and second low-frequency amplitudes. When high-frequency signal is input to a second electrode of the second elastic part, the peripheral part and the central part respectively vibrate with a first and second high-frequency amplitudes. A difference between the first and second low-frequency amplitudes is smaller than a difference between the first and second high-frequency amplitudes.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: December 31, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jen-Chieh Li, Chao-Ta Huang, Chung-Yuan Su, RueiHung Kao
  • Publication number: 20240405553
    Abstract: The present disclosure provides a scalable power distribution system including a power distribution device, the power distribution includes a plurality of input modules and a plurality of output modules. The input module includes a connector for receiving the input power. The output module has a plurality of output ports. The output module receives the input power of the connector of the corresponding input module, or receives the input power of the connector of the input module neighboring to the corresponding input module. The input module receives the plural types of input power, and the power distribution system selectively receives one or more times of the input power through one or more of the plurality of input modules to provide one or more times of the output power to one or more of the plurality of output ports.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Inventors: Chien-Lung Wu, I-Chieh Li, Yu-Chi Jen, Yen-Chun Wang, Hui-Ru Chen
  • Patent number: 12153088
    Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Chao Chieh Li, Yu-Tso Lin, Min-Shueh Yuan
  • Publication number: 20240385242
    Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, YU-TSO LIN, MIN-SHUEH YUAN
  • Publication number: 20240365560
    Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Mauricio Manfrini, Bo-Feng Young, Chun-Chieh Li, Han-Jong Chia, Sai-Hooi Yeong
  • Patent number: 12120885
    Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: October 15, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mauricio Manfrini, Bo-Feng Young, Chun-Chieh Li, Han-Jong Chia, Sai-Hooi Yeong
  • Publication number: 20240339432
    Abstract: A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Sung-Hui Huang, Shang-Yun Hou, Ying-Ching Shih, Cheng-Chieh Li
  • Patent number: 12096070
    Abstract: A video editing method applied to an electronic device is provided. The electronic device includes a processor and a human-machine interface, the processor is configured to execute a program to generate video data, and the human-machine interface is configured to receive an input signal. The video editing method includes: obtaining the video data; monitoring the input signal; setting an editing condition; and recording the video data to generate a video clip when the input signal meets the editing condition. A video editing system is further provided.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: September 17, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventor: Chieh Li
  • Publication number: 20240305302
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 12, 2024
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Publication number: 20240305301
    Abstract: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: CHAO CHIEH LI, CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHIH-HSIEN CHANG
  • Patent number: 12087727
    Abstract: A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Sung-Hui Huang, Shang-Yun Hou, Ying-Ching Shih, Cheng-Chieh Li
  • Publication number: 20240282896
    Abstract: A light-emitting unit includes a substrate, a light-emitting element, and a micro lens. The light-emitting element is disposed on the substrate. The micro lens surrounds the light-emitting element. The micro lens includes compound eye structures adjacent to each other. In a top view, each compound eye structure has a length and a width, and the light-emitting element has a length and a width. The length and width of each compound eye structure in the top view and the length and width of the light-emitting element in the top view substantially satisfy 1?(L1/W1)/(L2/W2)?1.5, in which W1 is the width of the light-emitting element in the top view, L1 is the length of the light-emitting element in the top view, W2 is the width of each compound eye structure in the top view, and L2 is the length of each compound eye structure in the top view.
    Type: Application
    Filed: August 16, 2023
    Publication date: August 22, 2024
    Inventors: Chun-Chieh LI, Han-Sheng NIAN, Hsin-Hung LI, Yu-Cheng SHIH
  • Patent number: 12069404
    Abstract: A video recording method applied to an electronic device is provided. The electronic device includes a processor configured to execute a program to generate video data. The video recording method includes: monitoring an operating parameter of the processor; setting a first condition; and starting obtaining the video data when the operating parameter meets the first condition. A video recording system is also provided.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: August 20, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventor: Chieh Li
  • Publication number: 20240241185
    Abstract: This disclosure provides an estimation method applied to a state of health of a battery, which executes a recharging to a battery when a battery voltage is lower than a threshold voltage. During the recharging, a battery state of health estimation procedure is performed from a first depth of discharge detection point to a second depth of discharge detection point. During the battery state of health estimation procedure, a voltage difference between a current battery voltage and an initial open-circuit voltage is accumulated over time from the first depth of discharge detection point to the second depth of discharge detection point to obtain an accumulation of current sampled voltage difference. An accumulation of estimated DC internal resistances can be equivalently obtained by the accumulation of current sampled voltage difference. Afterwards, the state of health of the battery can be determined based on the accumulation of estimated DC internal resistance.
    Type: Application
    Filed: July 11, 2023
    Publication date: July 18, 2024
    Inventors: Wen-Fan Chang, Chun-Chieh Li, Shih-Fa Hung, Jian-Min Chen
  • Patent number: 12021537
    Abstract: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Chih-Hsien Chang
  • Patent number: 11996852
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Publication number: 20240172359
    Abstract: Provided is a roughened copper foil capable of achieving both excellent transmission characteristics and high peel strength when used for a copper-clad laminate or a printed wiring board. This roughened copper foil includes a roughened surface on at least one side. The roughened surface has a roughness slope tan ? of 0.58 or less as calculated based on a mean height Rc (?m) and a mean width RSm (?m) of profile elements by formula Rc/(0.5×RSm), and a small projected area Rc×RSm of 0.45 ?m2 or more and 2.00 ?m2 or less that is a product of the mean height Rc (?m) and the mean width RSm (?m) of the profile elements. Rc and RSm are values measured in accordance with JIS B0601-2013 under a condition of not performing a cutoff by a cutoff value ?s and a cutoff value ?c.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 23, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Ayumu TATEOKA, Ryosuke KANEYAMA, Yasuji HARA, Yasuo SATO, Shinichi OBATA, Chun Chieh LI