Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Abstract: The present disclosure provides a scalable power distribution system including a power distribution device, the power distribution includes a plurality of input modules and a plurality of output modules. The input module includes a connector for receiving the input power. The output module has a plurality of output ports. The output module receives the input power of the connector of the corresponding input module, or receives the input power of the connector of the input module neighboring to the corresponding input module. The input module receives the plural types of input power, and the power distribution system selectively receives one or more times of the input power through one or more of the plurality of input modules to provide one or more times of the output power to one or more of the plurality of output ports.

Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.

Abstract: An AMHS interface management system configured to facilitate the exchange of lot information between distinct AMHS systems. The AMHS interface management system receives lot information from a first AMHS system in a first format and translates the lot information into a format associated with a second AMHS system. The AMHS interface management system utilizes a handshake area located between the first and second AMHS systems. The handshake area includes one or more vehicles that facilitate the movement of a lot between the first AMHS system and the second AMHS system.

Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.

Abstract: A backlight module includes a back board, a lamp board, a wavelength conversion film, an optical film, a coating layer and a reflective component. The back board includes a side wall. The lamp board is arranged on the back board, and includes plural light emitting units. The wavelength conversion film is arranged on the light emitting units. The optical film is arranged on the wavelength conversion film. The coating layer is arranged on the optical film, and adjacent to the optical film. The reflective component is arranged between the side wall and the optical film, and surrounds the wavelength conversion film and the optical film. At an optical wavelength of 450 nanometers, a brightness of a first surface of the reflective component is between 70 and 100, a first chromaticity thereof is between ?10 and 10, and a second chromaticity thereof is between ?10 and 10.

Abstract: A method, includes providing a wafer including a first surface grating extending over a first area of a surface of the wafer and a second surface grating extending over a second area of the surface of the wafer; de-functionalizing a portion of the surface grating in at least one of the first surface grating area and the second surface grating area; and singulating an eyepiece from the wafer, the eyepiece including a portion of the first surface grating area and a portion of the second surface grating area. The first surface grating in the eyepiece corresponds to an input coupling grating for a head-mounted display and the second surface grating corresponds to a pupil expander grating for the head-mounted display.

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.

Abstract: Disclosed are a gait analysis method, a gait analysis device, and a computer-readable storage medium. The method includes: obtaining consecutive N motion data; determining a plurality of probability distributions based on the N motion data, wherein the probability distributions respectively corresponds to a plurality of gait events; and determining an event time point of each gait event belonging to a specific step according to the plurality of probability distributions.

Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A display device includes a timing controller, a transmission line, and a source driver coupled to the timing controller via the transmission line. The source driver monitors a data rate of a pixel packet in an active area of a frame, synchronizes a clock according to the data rate to generate a synchronized clock, and clocks data in the pixel packet using the synchronized clock.

Abstract: An electronic device and a method of manufacturing an electronic device are provided. The electronic device includes an electronic component, a carrier, and a lead. The electronic component has a lateral surface. The carrier supports the electronic component. The lead is electrically connected to the electronic component and disposed adjacent to the lateral surface of the electronic component. The carrier and the lead are configured to block an electromagnetic wave between the electronic component and an external of the electronic device.

Abstract: A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.

Abstract: A system includes a first chuck operable to support a stencil including a plurality of apertures, a wafer chuck operable to support and move a wafer including a plurality of incoupling gratings, a first light source operable to direct light to impinge on a first surface of the stencil, and one or more second light sources operable to direct light to impinge on the wafer. The system also includes one or more lens and camera assemblies operable to receive light from the first light source passing through the plurality of apertures in the stencil and receive light from the one or more second light sources diffracted from the plurality of incoupling gratings in the wafer. The system also includes an alignment system operable to move the wafer with respect to the stencil to reduce an offset between aperture locations and incoupling grating locations.