Patents by Inventor Chieh LI

Chieh LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013492
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Sung-Hui Huang, Shang-Yun Hou, Ying-Ching Shih, Cheng-Chieh Li
  • Publication number: 20210372764
    Abstract: A system and a method for uniformed surface measurement are provided, in which a sensor is provided to perform measurements on a carrier in a polishing machine, and a measuring trajectory of the sensor on the carrier is adjusted by controlling the pivoting of a sensor carrier carrying the sensor and the rotation of a rotating platform in the polishing machine in order to achieve uniformed surface measurements of the carrier and real-time constructions of the surface topography. This allows the polishing state of the carrier to be monitored in real time, thereby improving the efficiency of the polishing process. A sensing apparatus for uniformed surface measurement is also provided.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Chao-Chang Chen, Jen-Chieh Li, Yong-Jie Ciou, Hsien-Ming Lee, Jian-Shian Lin, Chun-Chen Chen, Ching-Tang Hsueh
  • Patent number: 11170480
    Abstract: The present invention is directed to systems and methods for generating virtually averaged optical coherence tomography (Oct.) images. An illustrative method can include receiving an image, identifying a first voxel of the image, and selecting a plurality of local voxels of the image. Each of the plurality of local voxels is within a defined region of the first voxel. The values of the plurality of local voxels can indicate an appearance of the local voxels in the image.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: November 9, 2021
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Hiroshi Ishikawa, Chieh-Li Chen, Joel Steven Schuman, Chaim-Gadi Wollstein
  • Patent number: 11164855
    Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
  • Patent number: 11152330
    Abstract: A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Li, Pu Wang, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20210318780
    Abstract: A touch electrode is provided in the disclosure, including a first electrode layer and a second electrode layer. The first electrode layer includes a plurality of first electrodes. Each of the first electrodes includes a plurality of first electrode wires and a plurality of first axis wires, in which each of the first axis wires is connected to and perpendicular to the first electrode wires. The second electrode layer is electrically insulated and located above or beneath the first electrode layer. The second electrode layer includes a plurality of second electrodes. Each of the second electrodes includes a plurality of second electrode wires, and the second electrodes are spaced apart from each other and connected to each other in parallel. The material of the first and the second electrode layers is metal nanowires. A touch panel and a touch display, including the touch electrode described herein, are also provided.
    Type: Application
    Filed: March 19, 2021
    Publication date: October 14, 2021
    Inventors: Yi-Peng Gan, Cheng-Chieh Li, Qin-Xue Fang, Yong-Bin Ke, Si-Dian Chen
  • Patent number: 11139778
    Abstract: Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski
  • Publication number: 20210305940
    Abstract: Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Chao-Chieh LI, Robert Bogdan STASZEWSKI
  • Publication number: 20210242873
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Publication number: 20210225999
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Hao-chieh Chan
  • Patent number: 11063395
    Abstract: A cable connector disposed at a cable includes a signal protection device, an outer pipe and a transmission member. The signal protection device includes an inner pipe and a signal protection module. The inner pipe is inserted into the outer pipe through an end opening thereof such that a metallic conducting rod of the inner pipe is in the outer pipe. The signal protection module is inserted through another end opening of the outer pipe such that the metallic conducting rod of the inner pipe is penetratingly disposed at the signal protection module. The transmission member is inserted through another end opening of the outer pipe such that a conducting element is electrically connected to the metallic conducting rod of the inner pipe, revealing a transmission element. Therefore, the signal protection device is modularized and miniaturized.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: July 13, 2021
    Assignee: CABLESAT INTERNATIONAL CO., LTD.
    Inventor: Ching-Chieh Li
  • Publication number: 20210184681
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 17, 2021
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Patent number: 11031942
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10971577
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn. The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Hao-chieh Chan
  • Publication number: 20210082894
    Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
  • Publication number: 20210080503
    Abstract: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: CHAO CHIEH LI, CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHIH-HSIEN CHANG
  • Patent number: 10951026
    Abstract: A power distribution apparatus includes a power source terminal, a power-distributing module, at least a power distribution module, an input detection unit, at least an output detection unit and a management unit. The power source terminal receives an input power. The power-distributing module converts the input power into an output power. Each of the power distribution modules includes a plurality of output ports. The power distribution module receives the output power to output the output power through the output ports. The input detection unit detects the input power to generate a set of input information. The output detection unit detects the output power to generate at least a set of output information correspondingly. According to the input information or the output information, the management unit controls the output ports to be turned on or off correspondingly.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 16, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Chiang Chan, I-Chieh Li, Wen-Hsiang Lin
  • Publication number: 20210066867
    Abstract: A cable connector disposed at a cable includes a signal protection device, an outer pipe and a transmission member. The signal protection device includes an inner pipe and a signal protection module. The inner pipe is inserted into the outer pipe through an end opening thereof such that a metallic conducting rod of the inner pipe is in the outer pipe. The signal protection module is inserted through another end opening of the outer pipe such that the metallic conducting rod of the inner pipe is penetratingly disposed at the signal protection module. The transmission member is inserted through another end opening of the outer pipe such that a conducting element is electrically connected to the metallic conducting rod of the inner pipe, revealing a transmission element. Therefore, the signal protection device is modularized and miniaturized.
    Type: Application
    Filed: August 11, 2020
    Publication date: March 4, 2021
    Applicant: CABLESAT INTERNATIONAL CO., LTD.
    Inventor: Ching-Chieh LI
  • Patent number: 10931285
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Patent number: 10908086
    Abstract: A signal processing method and a signal processing system are provided to convert optical or electric signals by an effective circuit to have an increased dynamic contrast and reduced noises. The signal processing system includes an analog signal processing module and a digital signal processing module. When an optical signal of an object-to-be-detected is strong, an image-to-be-detected is obtained by an analog signal processing method. When the optical signal of the object-to-be-detected is weak, the image-to-be-detected is obtained by a digital signal processing method after background noises are filtered out.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 2, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Cho-Fan Hsieh, Feng-Chieh Li