Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

Abstract: A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.

Abstract: A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

Abstract: In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

Abstract: In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Abstract: In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.

Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.

Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.

Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

Abstract: A package structure includes a plurality of sub-package structures, a second encapsulant, a second RDL structure and a second conductive terminal. The sub-package structure includes a die, first TIVs, a first encapsulant and an antenna element. The die has a first side and a second side. The first TIVs are laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIVs. The antenna element is on the first side of the die, and on the TIVs and the first encapsulant. The second encapsulant encapsulates sidewalls of the sub-package structures. The second RDL structure is electrically connected to the plurality of sub-package structures. The second conductive terminal is electrically connected to the sub-package structures through the second RDL structure.

Abstract: A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a plurality of dies, a plurality of first conductive structures, an encapsulant, a second redistribution structure, and insulating layer, a plurality of second conductive structures, an antenna confinement structure, and a slot antenna. The dies and the first conductive structures are disposed on the first redistribution structure. The first conductive structures surround the dies. The encapsulant encapsulates the dies and the first conductive structures. The second redistribution structure is disposed on the dies, the first conductive structures, and the encapsulant. The insulating layer is over the second redistribution structure. The second conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.