Abstract: An illumination module includes a light source configured to emit an illumination light beam, a reflective light valve disposed on a path of the illumination light beam and configured to form a plurality of pixels, a lens, and an image sensing module. Each pixel is adapted to be switched between a first state and a second state. The pixels in the first state among the pixels are configured to reflect the illumination light beam into an effective light beam. The pixels in the second state among the pixels are configured to reflect the illumination light beam into a complementary light beam. The lens is disposed on a path of the effective light beam and configured to project the effective light beam to an area to be illuminated. The image sensing module is disposed on a path of a complementary light beam from the reflective light valve and configured to sense the complementary light beam.

Abstract: A wireless communication system comprises a transceiver, a housing, and a handle. The transceiver comprises an antenna. The housing has an interior volume. The handle is coupled to the housing externally from the interior volume, and the antenna is positioned within the handle.

Abstract: The present invention provides a transformed strain, comprising: a host cell; a first nucleotide sequence, located inside the host cell, the first nucleotide sequence encoding a PETase, which is derived from Ideonella; and a second nucleotide sequence, located inside the host cell, the second nucleotide sequence comprising a first chaperon nucleotide sequence or a second chaperon nucleotide sequence; wherein the first chaperon nucleotide sequence encodes a molecular chaperon protein (GroELS), and the second chaperon nucleotide sequence encodes a lipase secretion chaperone protein (LsC). The present invention also provides a method for degrading plastic, using said transformed strain for degrading a plastic having PET.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.

Abstract: A tracking system and a device integrating an existing positional tracking system and a docking mechanism include a tracking system hardware module, a docking mechanism, and a positional tracking software module and are adapted to capture a user's finger movement and send in real time and synchronously the user's finger movement to a computer. The docking mechanism is compatible with an existing third-party positional tracking system such that the device can operate in conjunction with existing, commercially-available positional tracking systems, for example, HTC VIVE Tracker, and Oculus Quest, and thus is applicable to an existing game engine.

Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Abstract: A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.

Abstract: Disclosed are a heat-electricity discrete power module with two-way heat-dissipation ceramic substrates and a manufacturing method of the same, including: two double-sided metal-clad ceramic substrates, a power transistor die, and an insulation sealant; each double-sided metal-clad ceramic substrate including a ceramic insulation layer, a three-dimensional conductive layer formed on the first ceramic insulation layer and facing the opposite three-dimensional conductive layer to constitute an electrical circuit, and a thermally-conductive metallic layer opposite and insulated from the three-dimensional conductive layer, respectively; electrodes of each power transistor die are electrically conductively connected to the three-dimensional conductive layer, and their upper and lower surfaces are thermally conductively connected to respective three-dimensional conductive layers; circuit components are additionally mounted on the three-dimensional conductive layers; at least one conductive post is formed between th

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: An electronic device includes a housing, an antenna structure, and a feeding element. The antenna structure includes a grounding element, a feeding radiation element, a switching circuit, and a first parasitic radiation element. The feeding radiation element includes a feeding portion, a first radiating portion, a second radiating portion, a first grounding arm, and a second grounding arm. The feeding portion is connected between the first radiating portion and the second radiating portion. The first grounding arm and the second grounding arm are connected to the first radiating portion. The switching circuit is electrically connected to the first grounding arm and the second grounding arm. The first parasitic radiation element is connected to the grounding element and coupled with the feeding radiation element.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A bus connection cable reverse-welding structure includes a circuit board, a flat cable, and a first line. The circuit board includes a wiring side, an insertion side, a welding area, a first mating area. A wire exit direction is defined from the wiring side toward the insertion side. The welding area is on the wiring side, and the first mating area is on the insertion side. The flat cable includes a main segment, an attached segment, and a welding end. The main segment extends along the wire exit direction, and the attached segment is attached on the circuit board. The welding end is electrically connected to the welding area. The first line is arranged in the circuit board and includes a first embedded segment and a first extension segment. The first embedded segment is embedded in the circuit board and connected to the welding area.

Abstract: A bus connection wire forward soldering structure includes a circuit board, a flat cable and a fixing member, and the circuit board has a solder area, a docking area, first and second surfaces and an outgoing line direction. The solder area is disposed on the first surface, the flat cable includes a solder terminal, first and second attaching sections, a folding section and a main body section, the solder terminal faces the docking area and is electrically connected to the solder area, the folding section is connected between the first and second attaching sections, the main body section extends along the outgoing line direction, the fixing member covers the solder terminal, the folding section, the first and second attaching sections, the fixing member has a notch defined corresponding to the second surface and located at junction of the second attaching section and the main body section junction.

Abstract: A method includes: forming a mask layer on a semiconductor wafer; forming a tin droplet, including: supplying tin to a high-pressure reservoir from a low-pressure reservoir; monitoring a level of tin in the high-pressure reservoir by at least two electrodes attached to the high-pressure reservoir; in response to the level of the tin exceeding a threshold value, supplying the tin to a droplet generator from the high-pressure reservoir; forming the tin droplet by the droplet generator using the tin supplied from the high-pressure reservoir; generating light by the tin droplet; and patterning the mask layer by the light.

Abstract: The present invention discloses a method of estimating a state of charge (SOC) of a battery and a system thereof. The method of estimating the SOC of the battery includes following steps: calculating a voltage difference (?V) using a voltaic gauge based on a battery voltage (VBAT) and an open-circuit voltage (OCV); adaptively adjusting a gain (K) using a gain control engine based on a battery current (IBAT) and a full charged capacity (FCC), wherein the gain (K) is adjusted to generate an adjusted gain (K?); generating a present SOC change (?SOC_T) using the voltaic gauge based on the voltage difference (?V) and the adjusted gain (K?); and generating a next SOC (SOC_T+1) using an accumulator based on a present SOC (SOC_T) and the present SOC change (?SOC_T).

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.

Abstract: A rotating direction and rotating speed sensing device includes a tested unit, a housing, and a Hall effect sensor disposed in the housing. The tested unit includes an output shaft, and a toothed disk sleeved on and driven by the output shaft. The Hall effect sensor positionally corresponds to the toothed disk for detecting rotating direction and rotating speed, and includes three Hall effect sensing elements spaced apart along a first straight line, and a first pin and a second pin respectively outputting a first signal and a second signal when the toothed disk rotates. The first straight line cooperates with a tangential direction of the toothed disk to form an included angle that ranges in a predetermined angle range, such that a phase shift between the first signal and the second signal ranges from 45 degrees to 135 degrees when the toothed disk rotates.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.