Patents by Inventor Chien An Lee

Chien An Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11435817
    Abstract: A multi-power management system and an operation method for the multi-power management system are provided. The multi-power management system includes multiple adapters and a power supply circuit. The adapters respectively provide multiple powers. The power supply circuit receives multiple input power values of the adapters, and calculates multiple input power value contribution ratios of the adapters according to the input power values. The power supply circuit further provides a control signal according to a sum of the output current values of multiple output current values of the powers and the input power value contribution ratios. The adapters adjust the output current values and multiple output voltage values respectively in response to the control signal.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 6, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chin-Hsiang Lin, Chien-Lee Liu, Tzu-Chiang Mi, Yi-Hsun Lin
  • Publication number: 20220256717
    Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 11, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Chia-Yu Peng, Shao-Chien Lee, Tzyy-Jang Tseng
  • Publication number: 20220240369
    Abstract: A circuit board includes a first dielectric material, a second dielectric material, a third dielectric material, a first external circuit layer, a second external circuit layer, multiple conductive structures, and a conductive via structure. Dielectric constants of the first, the second and the third dielectric materials are different. The first and the second external circuit layers are respectively disposed on the first and the third dielectric materials. The conductive via structure at least penetrates the first and the second dielectric materials and is electrically connected to the first and the second external circuit layers to define a signal path. The conductive structures are electrically connected to each other and surround the first, the second and the third dielectric materials. The conductive structures are electrically connected to the first and the second external circuit layers to define a ground path surrounding the signal path.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 28, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Chi-Min Chang, Shao-Chien Lee, Jun-Rui Huang, Ming-Ting Chang
  • Publication number: 20220232694
    Abstract: Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
    Type: Application
    Filed: October 8, 2021
    Publication date: July 21, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Heng-Ming Nien, Ching-Sheng Chen, Ching Chang, Ming-Ting Chang, Chi-Min Chang, Shao-Chien Lee, Jun-Rui Huang, Shih-Lian Cheng
  • Patent number: 11374349
    Abstract: A receptacle connector device for electrical vehicle use in accordance with the present invention is disposed at a battery terminal of an electric vehicle and is connected to a plug connector in a charging station. The receptacle connector comprises an insulating body and a plurality of conducting elements. The insulating body is made of waterproof plastic materials and the plurality of the conducting elements are made of metal materials. The insulating body has a plurality of concentric circular grooves and a transverse portion. The plurality of the conducting elements are respectively disposed in the plurality of the concentric circular grooves, characterized in that: each of the plurality of the conducting elements forms a rough surface, thereby to enlarge contact area between the plurality of the conducting elements and the insulating body in moulding process for firm combination of plastic and metal materials.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: June 28, 2022
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Sheng-Tsung Yuan
  • Publication number: 20220195245
    Abstract: Chemical Mechanical Planarization (CMP) polishing compositions, methods and systems are used to polish low-k or ultra-low-k films with reasonable high removal rates while to polish oxide and nitride films with relative low removal rates. The compositions use 5 abrasive, chemical additives to boost low-k or ultra-low-k film removal rates and suppress oxide and nitride film removal rates for achieving high selectivity, such as low-: TEOS, ultra-low-K: TEOS, and low-k: SiN or ultra-low-k: SiN.
    Type: Application
    Filed: April 16, 2020
    Publication date: June 23, 2022
    Applicant: Versum Materials US, LLC
    Inventors: Xiaobo Shi, Chia-Chien Lee, Mark Leonard O'Neill
  • Publication number: 20220095464
    Abstract: A circuit board includes a composite structure layer, at least one conductive structure, a thermally conductive substrate, and a thermal interface material layer. The composite structure layer has a cavity and includes a first structure layer, a second structure layer, and a connecting structure layer. The first structure layer includes at least one first conductive member, and the second structure layer includes at least one second conductive member. The cavity penetrates the first structure layer and the connecting structure layer to expose the second conductive member. The conductive structure at least penetrates the connecting structure layer and is electrically connected to the first conductive member and the second conductive member. The thermal interface material layer is disposed between the composite structure layer and the thermally conductive substrate, and the second structure layer is connected to the thermally conductive substrate through the thermal interface material layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: March 24, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Shao-Chien Lee, Ra-Min Tain, Chi-Chun Po, Po-Hsiang Wang, Pei-Chang Huang, Chin-Min Hu
  • Publication number: 20220072070
    Abstract: Disclosed herein is a composition including Lactobacillus plantarum TWK10 deposited at the China General Microbiological Culture Collection Center (CGMCC) under accession number CGMCC 13008 for use in improving walking capacity of an elderly subject.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 10, 2022
    Inventors: Chia-Chia LEE, Han-Yin HSU, Chi-Chang HUANG, Yi-Ju HSU, Mon-Chien LEE
  • Publication number: 20220071015
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 3, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Publication number: 20220071000
    Abstract: The disclosure provides a circuit board structure including at least two sub-circuit boards and at least one connector. Each of the sub-circuit boards includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.
    Type: Application
    Filed: January 14, 2021
    Publication date: March 3, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Publication number: 20220071010
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.
    Type: Application
    Filed: September 26, 2021
    Publication date: March 3, 2022
    Inventors: Tzyy-Jang TSENG, Cheng-Ta KO, Pu-Ju LIN, Chi-Hai KUO, Shao-Chien LEE, Ming-Ru CHEN, Cheng-Chung LO
  • Publication number: 20220044478
    Abstract: The photo-video based spatial-temporal volumetric capture system more efficiently, produces high frame rate and high resolution 4D dynamic human videos, without a need for 2 separate 3D and 4D scanner systems, by combining a set of high frame rate machine vision video cameras with a set of high resolution photography cameras. It reduces a need for manual CG works, by temporally up-sampling shape and texture resolution of 4D scanned video data from a temporally sparse set of higher resolution 3D scanned keyframes that are reconstructed both by using machine vision cameras and photography cameras. Unlike typical performance capture system that uses single static template model at initialization (e.g. A or pose), the photo-video based spatial-temporal volumetric capture system stores multiple keyframes of high resolution 3D template models for robust and dynamic shape and texture refinement of 4D scanned video sequence.
    Type: Application
    Filed: December 20, 2019
    Publication date: February 10, 2022
    Inventors: Kenji Tashiro, Chuen-Chien Lee, Qing Zhang
  • Patent number: 11235797
    Abstract: A child transporter includes a seat and a canopy. The canopy is disposed above the seat, and includes an air channel configured to direct a wind curtain about the seat.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: February 1, 2022
    Inventor: Curtis Chien Lee
  • Publication number: 20210373621
    Abstract: A stacked computer system includes a main machine module and expansion modules detachably stacked with each other. Each of the expansion modules is electrically connected to the main machine module. Each of the main machine module and the expansion modules includes a first connector located at an upper position and a second connector located at a lower position. In any two of the main machine module and the expansion modules adjacent to each other, the first connector of a lower one is connected to the second connector of the other one. Each of the first connector and the second connector includes at least two of a data transmission control interface, a power supply interface, a display signal transmission interface and a detection interface.
    Type: Application
    Filed: March 8, 2021
    Publication date: December 2, 2021
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Ching-Hsun Huang, Tse-Hsien Liao, Chin-Hui Chen, Erh-Chia Joung, Yuan-Liang Chen, Chun-Chien Lee, Po-Jen Shih
  • Publication number: 20210351088
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 11, 2021
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Patent number: 11157048
    Abstract: A memory module with a screen includes a memory substrate, a power conversion module, a screen control module, and a screen. The memory substrate includes a plurality of memory components and a connection interface. The power conversion module is disposed on the memory substrate and electrically connected to the connection interface. The screen control module is disposed on the memory substrate and electrically connected to the connection interface and the power conversion module. The screen is disposed on the memory substrate, and the screen is electrically connected to the power conversion module and the screen control module to receive a voltage output from the power conversion module and a display signal output from the screen control module. A motherboard module including a memory module with a screen is also provided.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 26, 2021
    Assignee: GAGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Hung-Cheng Chen, Tse-Hsien Liao, Chun-Chien Lee, Chen-Te Hsu
  • Publication number: 20210325959
    Abstract: A multi-power management system and an operation method for the multi-power management system are provided. The multi-power management system includes multiple adapters and a power supply circuit. The adapters respectively provide multiple powers. The power supply circuit receives multiple input power values of the adapters, and calculates multiple input power value contribution ratios of the adapters according to the input power values. The power supply circuit further provides a control signal according to a sum of the output current values of multiple output current values of the powers and the input power value contribution ratios. The adapters adjust the output current values and multiple output voltage values respectively in response to the control signal.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 21, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chin-Hsiang Lin, Chien-Lee Liu, Tzu-Chiang Mi, Yi-Hsun Lin
  • Patent number: 11114782
    Abstract: A circuit board structure has a first flexible circuit board, a second flexible circuit board, and a rigid board structure. The first flexible circuit board has a first dielectric layer and a first conductive circuit. The second flexible circuit board has a second dielectric layer and a second conductive circuit. The rigid board structure connects the first flexible circuit board and the second flexible circuit board. The rigid board structure has a third dielectric layer and a third conductive circuit. A dielectric loss value of the third dielectric layer is less than that of each of the first dielectric layer and the second dielectric layer. The third conductive circuit is electrically connected to the first and second conductive circuits.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: September 7, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Ching-Ho Hsieh, Shao-Chien Lee, Kuo-Wei Li
  • Patent number: D952551
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 24, 2022
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Chung-Hui Chen, Chien-An Lee, Ming Che Chan, Shen-Yuan Chien, Tannan Whidden Winter
  • Patent number: D961511
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: August 23, 2022
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Chung-Hui Chen, Chien-An Lee, Ming Che Chan, Shen-Yuan Chien, Tannan Whidden Winter