Patents by Inventor Chien-An Yu
Chien-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176320Abstract: A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.Type: GrantFiled: March 23, 2022Date of Patent: December 24, 2024Assignee: AP MEMORY TECHNOLOGY CORPORATIONInventors: Wenliang Chen, Chien An Yu
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Publication number: 20240371747Abstract: A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Applicant: AP Memory Technology Corp.Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
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Patent number: 12074103Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.Type: GrantFiled: June 1, 2022Date of Patent: August 27, 2024Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien-An Yu, Chun Yi Lin
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Patent number: 11652011Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.Type: GrantFiled: August 12, 2021Date of Patent: May 16, 2023Assignee: AP Memory Technology Corp.Inventors: Wen Liang Chen, Lin Ma, Chien-An Yu, Chun Yi Lin
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Publication number: 20220359456Abstract: A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.Type: ApplicationFiled: March 23, 2022Publication date: November 10, 2022Inventors: WENLIANG CHEN, CHIEN AN YU
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Publication number: 20220302021Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.Type: ApplicationFiled: June 1, 2022Publication date: September 22, 2022Applicant: AP Memory Technology Corp.Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
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Patent number: 11417628Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: GrantFiled: September 1, 2020Date of Patent: August 16, 2022Assignee: AP Memory Technology CorporationInventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien An Yu, Chun Yi Lin
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Patent number: 11380614Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.Type: GrantFiled: September 2, 2020Date of Patent: July 5, 2022Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien-An Yu, Chun Yi Lin
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Publication number: 20210398943Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: ApplicationFiled: September 1, 2020Publication date: December 23, 2021Inventors: WENLIANG CHEN, JUN GU, MASARU HARAGUCHI, TAKASHI KUBO, CHIEN AN YU, CHUN YI LIN
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Publication number: 20210375705Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicant: AP Memory Technology Corp.Inventors: Wen Liang CHEN, Lin MA, Chien-An YU, Chun Yi LIN
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Patent number: 11158552Abstract: A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers.Type: GrantFiled: June 11, 2020Date of Patent: October 26, 2021Assignee: AP Memory Technology Corp.Inventors: Wen Liang Chen, Lin Ma, Chien-An Yu, Chun Yi Lin
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Publication number: 20200402903Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: AP Memory Technology Corp.Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
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Publication number: 20200402951Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.Type: ApplicationFiled: September 1, 2020Publication date: December 24, 2020Inventors: WENLIANG CHEN, JUN GU, MASARU HARAGUCHI, TAKASHI KUBO, CHIEN AN YU, CHUN YI LIN
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Publication number: 20200357709Abstract: A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers.Type: ApplicationFiled: June 11, 2020Publication date: November 12, 2020Applicant: AP Memory Technology Corp.Inventors: Wen Liang CHEN, Lin MA, Chien-An YU, Chun Yi LIN
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Publication number: 20190088488Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. A first insulation layer is formed to cover the transistor. The first insulation layer is patterned to form at least one opening, wherein a part of the transistor is exposed by the opening. At last, an epitaxy is formed in the opening to cover the part of the transistor.Type: ApplicationFiled: November 15, 2018Publication date: March 21, 2019Inventors: Hung-Yu CHI, Chien-An YU, Yi-Fong LIN, Feng-Ling CHEN
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Publication number: 20170133230Abstract: A semiconductor device includes a transistor disposed on a substrate, a first insulation layer, a second insulation layer, an epitaxy and a conductive material. The first insulation layer is disposed on the substrate and protruding over the transistor. The first insulation layer has a recess to expose a top portion of the transistor. The second insulation layer is disposed on the first insulation layer and conforms to the recess and exposes the top portion of the transistor. The epitaxy is disposed in the recess of the first insulation layer and overlaps the top portion of the transistor. The epitaxy conforms to sidewalls of the recess of the first insulation layer. The conductive material is disposed in the recess of the first insulation layer.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventors: Hung-Yu CHI, Chien-An YU, Yi-Fong LIN, Feng-Ling CHEN
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Patent number: 9153665Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.Type: GrantFiled: March 11, 2013Date of Patent: October 6, 2015Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chien-An Yu, Yuan-Sung Chang, Yi-Fong Lin, Chin-Piao Chang, Chih-Huang Wu, Wen-Chieh Wang
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Patent number: 9041154Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.Type: GrantFiled: March 6, 2013Date of Patent: May 26, 2015Assignee: NANYA TECHNOLOGY CORP.Inventors: Chien-An Yu, Chih-Huang Wu
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Publication number: 20150097228Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. A first insulation layer is formed to cover the transistor. The first insulation layer is patterned to form at least one opening, wherein a part of the transistor is exposed by the opening. At last, an epitaxy is formed in the opening to cover the part of the transistor.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Hung-Yu CHI, Chien-An YU, Yi-Fong LIN, Feng-Ling CHEN
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Patent number: 8962411Abstract: A method of manufacturing a circuit pattern with high aspect ratio is disclosed. A plurality of parallel lines and supporting lines intersecting the parallel lines are formed. Supporting isolation structures are then formed in the space between the parallel lines and the supporting line for supporting the parallel lines in a later etching process. The parallel lines and the supporting line are then disconnected after the etching process.Type: GrantFiled: August 9, 2012Date of Patent: February 24, 2015Assignee: Nanya Technology Corp.Inventors: Chien-An Yu, Yi-Fong Lin