Abstract: An electronic system is provided. The electronic system includes a processor and a first power management circuit. The processor generates and outputs a first data frame. The first data frame includes at least one first guard bit and a first address. The first power management circuit includes a first register. The first power management circuit receives the first data frame and determines legitimacy of the first address according to the least one first guard bit. In response to that the first address is legal, the power management circuit transmits a first response to the processor and accesses a first region in the first register according to the first address.

Abstract: An insulation resistance detection system for an electric vehicle is used to detect a positive insulation resistance between a positive electrode of a battery of the electric vehicle and an equipment grounding point, and detect a negative insulation resistance between a negative electrode of the battery and the equipment grounding point. The insulation resistance detection system includes a negative detection circuit, a positive detection circuit, and a control unit. The control unit controls the negative detection circuit to be charged to generate a first capacitor voltage, and controls the positive detection circuit to be charged to generate a second capacitor voltage. The control unit determines whether the negative insulation resistance is abnormal according to the first capacitor voltage and a battery voltage of the battery, and determines whether the positive insulation resistance is abnormal according to the second capacitor voltage and the battery voltage.

Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A photodetecting device is provided. The photodetecting device includes a silicon substrate, a germanium absorption region, and a plurality of microstructures. The silicon substrate includes a first surface and a second surface. The germanium absorption region is formed proximal to the first surface of the silicon substrate, and the germanium absorption region is configured to absorb photons and to generate photo-carriers. The plurality of microstructures are formed over the second surface of the silicon substrate, and the plurality of microstructures are configured to direct an optical signal towards the germanium absorption region. A system including an optical transmitter and an optical receiver is also provided.

Abstract: A heat dissipation device is provided and includes: a casing; a base unit combined with the casing to form a water collecting chamber, a water inlet chamber, an action space and a water outlet chamber; a heat transfer structure disposed on an inner side of the base unit; a water inlet pipeline unit communicated with the water collecting chamber; a water outlet pipeline unit communicated with the water outlet chamber; and a pump unit disposed outside the casing and the base unit, and connected with the water inlet pipeline unit and the water outlet pipeline unit, so as to drive a working medium.

Abstract: A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

Abstract: A pulsed-DC power generator is used to sputter a substrate in a chamber, and the power generator includes a first voltage source, a second voltage source, a switch unit, a control unit, and a detection unit. The control unit provides a first control signal to control the switching of the switch unit to integrate a first voltage of the first voltage source and a second voltage of the second voltage source into a pulse voltage. The control unit adjusts parameters of a first predetermined time period for arc extinction when the pulse voltage is in a working time period of the first voltage, and the number that a voltage value of the first voltage in a voltage variation to be higher than a range is higher than the number of occurrence.

Abstract: The present disclosure relates to a composition for inducing immune response comprising a glycoengineered antibody or antigen-binding fragment thereof that is specific for an antigen portion having a receptor binding domain (RBD) of a surface protein of a virus. The present disclosure also relates to an immune combination and a method for treating an infection by a virus.

Abstract: A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a plurality of second guiding members. The first movable portion is configured to connect an optical member. The optical member is used for adjusting a direction of a light from an incident direction to an outgoing direction. The first movable portion can move relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion. The second guiding members include a first ball, a second ball, and a third ball. The first ball, the second ball, and the third ball are disposed in a plane that is perpendicular to the incident direction.

Abstract: Provided is a semiconductor structure including a circuit layer, an island-shaped conductive layer, a MRAM cell, a bit line and a conductive via. The circuit layer is disposed on a substrate. The island-shaped conductive layer is disposed on the circuit layer. The MRAM cell is disposed between the island-shaped conductive layer and the circuit layer, and is electrically connected to the island-shaped conductive layer and the circuit layer. The bit line is disposed on the island-shaped conductive layer. The conductive via is disposed between the bit line and the island-shaped conductive layer. The island-shaped conductive layer is in contact with a top surface of the MRAM cell.

Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

Abstract: A memory device is provided, including at least one inverter, a transistor coupled between the at least one inverter and a bit line, and an assist circuit coupled to the bit line, configured to provide a negative voltage to the bit line, and configured to pull down a power supply voltage provided to the at least one inverter.

Abstract: A method includes forming a fin structure including a first channel layer, a sacrificial layer, and a second channel layer over a substrate; forming a dummy gate structure across the fin structure; recessing the fin structure; epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer; forming first dielectric layers to cover the first source/drain epitaxial structures, respectively; epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer; removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and forming a metal gate structure in the gate trench. The second source/drain epitaxial structures are over the first dielectric layers, respectively.

Abstract: A board-to-board connector includes an insulating body and a conductive terminal. The conductive terminal includes a mounting portion, a first resilient arm and a second resilient arm. The mounting portion includes a main body portion and at least one tab protruding from the main body portion. The first resilient arm includes a first connecting portion, a first elastic arm, a first contact portion, a first extension arm and a first end portion. The second resilient arm includes a second connecting portion, a second elastic arm, a second contact portion, a second extension arm and a second end portion. When the first circuit board and the second circuit board abut against the corresponding first contact portion and the second contact portion, the first extension arm is in contact with the second end portion and/or the second extension arm is in contact with the first end portion.

Abstract: A glass manufacturing apparatus includes an exit conduit positioned to deliver molten glass from a delivery vessel to an inlet conduit of a forming apparatus. The apparatus also includes a leak blocking component that circumferentially surrounds a portion of the exit conduit and is configured to inhibit flow of molten glass towards an outer surface of the glass manufacturing apparatus.

Abstract: A method for fabricating an integrated circuit device includes forming first epitaxial stack comprising a first sacrificial layer and a first channel layer over a substrate; forming a second epitaxial stack comprising a second sacrificial layer and a second channel layer over the first epitaxial stack; etching a recess in the first and second epitaxial stacks, wherein the recess exposes end surfaces of the first and second channel layers; performing a first ion implantation process to form a first lightly doped region; performing a second ion implantation process to form a second lightly doped region, wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process; forming first and second source/drain epitaxial features in the recess; and replacing the first and the second sacrificial layers with a high-k/metal gate structure.

Abstract: A cantilever for gas flow direction control configured to support an electrode housing bowl in an associated etch process chamber. The cantilever may have a cross-section that is circular, elliptical, or airfoil shaped. The shape of the cantilever induces the flow of gas and etch products within the chamber around the cantilever, reducing turbulence around the edge of a wafer.

Abstract: A two-phase cold plate includes a base, an upper cover, a heat exchange cavity and a cooling fin module. The upper cover is installed on the base, the heat exchange cavity is formed between the base and the upper cover, and the cooling fin module is installed in the heat exchange cavity. The upper cover includes at least one nozzle module and a plurality of two-phase fluid channels. The two-phase fluid channels are respectively located on both sides of the nozzle module, and the nozzle module sprays a heat dissipating fluid to the cooling fin module, and the heat dissipating fluid flows along the cooling fin module to the two-phase fluid channels on both sides of the cooling fin module to cool the cooling fin module.