Patents by Inventor Chien-Chang Lee
Chien-Chang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220269003Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.Type: ApplicationFiled: May 9, 2022Publication date: August 25, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
-
Publication number: 20220155527Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Yueh Ying LEE, Chien-Ying WU, Sui-Ying HSU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
-
Patent number: 11327228Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.Type: GrantFiled: July 9, 2020Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
-
Publication number: 20220011511Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
-
Patent number: 11175452Abstract: A method for fabricating a photonic device is provided. The method includes patterning a semiconductor layer to form a waveguide structure, a semiconductor structure connected to the waveguide structure, and a dummy semiconductor structure disconnected from the waveguide structure and the semiconductor structure; epitaxially growing an epitaxial semiconductor feature over the semiconductor structure and a dummy epitaxial semiconductor feature over the dummy semiconductor structure; depositing a first capping film over the epitaxial semiconductor feature and the dummy epitaxial semiconductor feature; depositing a second capping film over the first capping film, wherein an oxide concentration of the second capping film is greater than an oxide concentration of the first capping film; and patterning the first and second capping films to form at least a dummy composite capping layer over the dummy epitaxial semiconductor feature.Type: GrantFiled: August 11, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
-
Patent number: 10063268Abstract: In certain embodiments of the present invention, a portable electronic device support comprises a base, a frame, and a rotational mechanism, with the base including a front and a rear panel. The rotational mechanism is attached to the frame at a position offset from the center so that substantially the same viewing angle can be maintained after rotation from landscape to portrait orientation.Type: GrantFiled: April 6, 2015Date of Patent: August 28, 2018Assignee: Logitech Europe S.A.Inventors: Kim Gygax, Yibo Shao, Li Lun Wen, Chien-Chang Lee, Jacky Wu
-
Patent number: 9995770Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.Type: GrantFiled: March 21, 2014Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tseng-Chin Lo, Huan Chi Tseng, Kuo-Chuan Chang, Yuan-Yao Chang, Chien-Chang Lee
-
Patent number: 9762279Abstract: Embodiments of the invention show a tablet cover that folds to provide a stand for the tablet. A friction hinge between two sections of the tablet cover provides sufficient friction to maintain the stand at the desired angle. In order to allow the cover to be easily flattened after use, a release mechanism is provided in the friction hinge.Type: GrantFiled: September 30, 2015Date of Patent: September 12, 2017Assignee: Logitech Europe S.A.Inventors: Chia Feng Lee, Chien-Chang Lee
-
Publication number: 20160241987Abstract: The present disclosure relates to an operation and management system providing applications for mobile devices and an electronic transaction method and an application generator thereof.Type: ApplicationFiled: October 9, 2014Publication date: August 18, 2016Inventors: KUEN-MOU LEE, CHIEN-CHANG LEE, TA-WEI LIN, CHAO-CHI LEE, HUI-FEN FANG, CHIH-HUNG LIN, WEI-WEI CHEN
-
Publication number: 20160134322Abstract: Embodiments of the invention show a tablet cover that folds to provide a stand for the tablet. A friction hinge between two sections of the tablet cover provides sufficient friction to maintain the stand at the desired angle. In order to allow the cover to be easily flattened after use, a release mechanism is provided in the friction hinge.Type: ApplicationFiled: September 30, 2015Publication date: May 12, 2016Applicant: Logitech Europe S.A.Inventors: Chia Feng Lee, Chien-Chang LEE
-
Publication number: 20150288405Abstract: In certain embodiments of the present invention, a portable electronic device support comprises a base, a frame, and a rotational mechanism, with the base including a front and a rear panel. The rotational mechanism is attached to the frame at a position offset from the center so that substantially the same viewing angle can be maintained after rotation from landscape to portrait orientation.Type: ApplicationFiled: April 6, 2015Publication date: October 8, 2015Inventors: Kim Gygax, Yibo Shao, Li Lun Wen, Chien-Chang Lee, Jacky Wu
-
Patent number: 9151798Abstract: Provided is an apparatus for testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices.Type: GrantFiled: July 28, 2011Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih Jie Shao, Tang-Hsuan Chung, Szu-Chia Huang, Huan Chi Tseng, Chien-Chang Lee, Yu-Lan Hsiao
-
Publication number: 20150268271Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tseng-Chin Lo, Huan Chi Tseng, Kuo-Chuan Chang, Yuan-Yao Chang, Chien-Chang Lee
-
Patent number: 8674355Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.Type: GrantFiled: December 29, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
-
Publication number: 20130027075Abstract: The present disclosure provides an apparatus testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhih Jie Shao, Tang-Hsuan Chung, Szu-Chia Huang, Huan Chi Tseng, Chien-Chang Lee, Yu-Lan Hsiao
-
Publication number: 20120168751Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
-
Patent number: 7825678Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.Type: GrantFiled: August 22, 2008Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Tseng Chin Lo, Chien-Chang Lee, Chih-Chieh Shao
-
Publication number: 20100245740Abstract: A transflective LCD panel and a manufacturing method for lower substrate thereof are provided. The transflective LCD panel includes an upper substrate, a liquid crystal layer and a lower substrate. The liquid crystal layer, including a plurality of liquid crystal molecules, is disposed between the upper substrate and the lower substrate. The lower substrate includes an active array structure layer, a plurality of transparent pixel electrodes and a cushion layer. The active array structure layer includes a plurality of transparent bottom electrodes, transistor structures and an insulation layer. The insulation layer covers the transparent bottom electrode. The transparent pixel electrodes are formed on the active array structure layer, wherein each transparent pixel electrode partially overlaps the corresponding transparent bottom electrode and the overlap is located at the transmissive region.Type: ApplicationFiled: March 24, 2010Publication date: September 30, 2010Applicant: WINTEK CORPORATIONInventors: Hsiu-Lin Chan, Cheng-Yen Yeh, Chien-Chang Lee
-
Patent number: D744491Type: GrantFiled: November 10, 2014Date of Patent: December 1, 2015Assignee: Logitech Europe S.A.Inventors: Chia Feng Lee, Chien-Chang Lee
-
Patent number: D761798Type: GrantFiled: October 26, 2015Date of Patent: July 19, 2016Assignee: Logitech Europe S.A.Inventors: Chia Feng Lee, Chien-Chang Lee