Abstract: The present disclosure provides a photomask, including a plurality of pattern areas, each of the pattern areas is defined by a respective boundary, a first pattern area including a first mask feature, and a training area adjacent to a boundary of the pattern area, the training area comprising a first training feature, wherein the first training feature is comparable to the first mask feature.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one or more color filters placed above the top electrode, wherein the porous or low density dielectric region contains light emitting nanocrystal materials.

Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

Abstract: An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask.

Abstract: A method for fabricating a patterned layer is disclosed. Firstly, a semiconductor substrate is provided. Then, a precursory gas on the semiconductor substrate is formed. Finally, a patterned layer on the semiconductor substrate is deposited by reacting the precursory gas with at least one electron beam or at least one ion beam. The present invention not only fabricates a patterned layer on the substrate in a single step but also achieves a high lithographic resolution and avoids remains of contaminations by using the properties of the electron beam or the ion beam and the precursory gas.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Abstract: The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.

Abstract: The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.

Abstract: A system separating defective dies from a wafer comprises a film frame platform and a pick-and-place device. The film frame platform comprises a support table assembly configured for supporting a film frame assembly and a platform surface configured to receive the placement of bins thereupon. The pick-and-place device is configured for moving in a linear manner between the support table assembly and the platform surface.

Abstract: A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.