Patents by Inventor Chien-Chen Ko
Chien-Chen Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344292Abstract: The disclosure provides a semiconductor chip suit for driving a display panel. The semiconductor chip includes a first pad group and a second pad group. The first pad group and the second pad group are disposed at a first long side of the semiconductor chip. The first distance from the first pad group to the edge of the first long side is different from the second distance from the second pad group to the edge of the first long side. The first pad group and the second pad group belong to a first pad row disposed at the first long side. The first pad group comprises a plurality of pads which are closer to the middle of the first pad row than the second pad group.Type: ApplicationFiled: April 25, 2022Publication date: October 27, 2022Applicant: Novatek Microelectronics Corp.Inventors: Huan-Teng Cheng, Huang-Chin Tang, Chien-Chen Ko
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Patent number: 11444058Abstract: A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.Type: GrantFiled: January 20, 2021Date of Patent: September 13, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Chien-Chen Ko, Teng-Jui Yu, Wei-Kang Tsai
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Publication number: 20220149006Abstract: A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.Type: ApplicationFiled: January 20, 2021Publication date: May 12, 2022Inventors: Chien-Chen KO, Teng-Jui YU, Wei-Kang TSAI
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Patent number: 10643921Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.Type: GrantFiled: August 6, 2019Date of Patent: May 5, 2020Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko, Ling-Chieh Li
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Publication number: 20190363032Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko, Ling-Chieh Li
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Publication number: 20190287931Abstract: A chip on film package including a base film, a patterned circuit layer, a chip, an underfill portion, and a water resistant layer. The base film includes a first surface and a second surface opposite to the first surface, and the first surface includes a mounting region. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The underfill portion covers a connecting portion where the chip and the pattern circuit layer are connected. The water resistant layer at least coves an outer surface of the underfill, wherein the material of the water resistant layer includes resin and metal particles.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Applicant: Novatek Microelectronics Corp.Inventors: Chien-Chen Ko, Chiao-Ling Huang
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Patent number: 10418305Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.Type: GrantFiled: January 30, 2019Date of Patent: September 17, 2019Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko, Ling-Chieh Li
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Publication number: 20190198417Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.Type: ApplicationFiled: January 30, 2019Publication date: June 27, 2019Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko, Ling-Chieh Li
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Patent number: 10236234Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.Type: GrantFiled: February 23, 2018Date of Patent: March 19, 2019Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko
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Patent number: 10079194Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.Type: GrantFiled: June 5, 2017Date of Patent: September 18, 2018Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko
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Publication number: 20180261524Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.Type: ApplicationFiled: February 23, 2018Publication date: September 13, 2018Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko
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Publication number: 20180261523Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.Type: ApplicationFiled: June 5, 2017Publication date: September 13, 2018Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Chien-Chen Ko