Abstract: A computer vision processing system is provided. The system includes one or more target devices and a processing unit. The target devices are configured to run the executable code of an image processing pipeline. The processing unit is configured to receive a series of application programming interface (API) calls and create a raw graph accordingly, redraw the raw graph into a compilable graph by sequentially processing each node, and compile the compilable graph into the executable code of the image processing pipeline. The series of API calls includes at least one tiling API call to set at least one of the nodes and at least one of the data objects as tileable. Each tileable node corresponds to multiple parallel processing nodes in multiple branches in the compilable graph, and each tileable data object corresponds to multiple tile data objects in the branches in the compilable graph.

Abstract: A multi-power system for providing electrical energy includes a fuel cell unit, a lithium-ion cell unit, and a control unit. The control unit stores a power optimization data sheet that includes multiple power parameter sets, each including a first optimal power and a second optimal power. The control unit is configured to, when operating in a specific mode, select one of the power parameter sets as a selected set, control the fuel cell unit to operate at the first optimal power included in the selected set, control the lithium-ion cell unit to operate at the second optimal power included in the selected set, and control the fuel cell unit and the lithium-ion cell unit to cooperatively output electricity.

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Abstract: A method and apparatus for determining a BFD RS are provided. The method includes receiving at least one MAC CE for TCI state activation, each MAC CE indicating a CORESET and at least one TCI state, at least a subset of the indicated TCI state(s) belonging to a first group of TCI states associated with a first TRP; and performing first operations after determining that a total number of TCI states included in the first group of TCI states is larger than a first threshold number, the first operations including: selecting at least one first TCI state from the first group of TCI states; and determining at least one first BFD RS for detecting a first beam failure condition of the first TRP based on the at least one first TCI state.

Abstract: A method for a user equipment (UE) for performing a hybrid automatic repeat request (HARQ) codebook generation operation for downlink transmission(s) is disclosed. The method comprises receiving, from a base station, a dynamic scheduling configuration for HARQ feedback operation; receiving, from the base station, a scheduling signaling for a first physical downlink shared channel (PDSCH) reception with a first HARQ state feedback for the first PDSCH reception being disabled; and generating, for the HARQ feedback operation, a HARQ codebook excluding a first HARQ state for the first PDSCH reception.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: A memory device is provided. The memory device comprises a memory cell, a first power rail and a suppressing circuit. The memory cell is coupled to a word line. The first power rail transmits a first supply voltage. The suppressing circuit comprises a first transistor and a second transistor. The first transistor is diode-connected, coupled to the word line, and disposed at a first layer. The second transistor is diode-connected coupled between the first transistor and the first power rail, and disposed at a second layer under the first layer. The first transistor and the second transistor overlap with each other in a layout view.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: A memory cell includes a first and second transmission pass-gate, a read word line and a write word line. The first transmission pass-gate includes a first and second pass-gate transistor. The second transmission pass-gate includes a third and fourth pass-gate transistor. The read word line is on a first metal layer above a front-side of a substrate. The write word line is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation. The second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: Provided is a method for treating or preventing hair loss or facilitating hair growth or regrowth. More particularly, it relates to a composition for preventing or treating hair loss and/or facilitating hair growth on the scalp and/or skin of a subject in need thereof. The composition includes an effective amount of a polypeptide or a nucleic acid molecule encoding the polypeptide, and the polypeptide comprises an amino acid sequence having an EGF-like domain of thrombomodulin or a conservative variant thereof.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.