Abstract: A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.

Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has a photonic crystal structure. The insulating layer is disposed on an upper surface and a sidewall surface of the first platform, and on an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, the active layer, and at least a portion of the first waveguiding layer. The first electrode is on the insulating layer and the second electrode is connected to the outer surface of the substrate and arranged to form an opening for laser output.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Abstract: A memory cell includes a first and second transmission pass-gate, a read word line and a write word line. The first transmission pass-gate includes a first and second pass-gate transistor. The second transmission pass-gate includes a third and fourth pass-gate transistor. The read word line is on a first metal layer above a front-side of a substrate. The write word line is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation. The second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on.

Abstract: A package structure includes a package substrate, a semiconductor die module on the package substrate, a ring structure on the package substrate adjacent to the semiconductor die module, and a hybrid adhesive having a first modulus and a second modulus less than the first modulus and attaching the ring structure to the package substrate.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Abstract: An image generation method and an image generation device are disclosed. The method includes: reading a first image from a storage circuit; disposing an image mask on the first image, wherein the image mask covers a part of the image areas in the first image; moving, randomly, the image mask to change a covering range of the image mask in the first image; obtaining a second image from the first image according to the moved image mask; and storing the second image into the storage circuit.

Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.

Abstract: An embodiment semiconductor package structure may include a package substrate, a semiconductor die coupled to the package substrate, and a package lid attached to the package substrate and covering the semiconductor die. The package lid may include a top portion having a spatially varying thermal conductivity that is greater in a first region than in a second region. The first region may include a multi-layer structure including a metal/diamond composite material supported by a copper layer. The metal/diamond composite material may include a silver/diamond, copper/diamond, or aluminum/diamond material and may have a thermal conductivity that is within a range from 600 W/m·K to 900 W/m·K and a coefficient of thermal expansion that is in a second range from 5 ppm/° C. to 10 ppm/° C. The package lid may have an effective coefficient of thermal expansion that is in a range from 14.5 ppm/° C. to 17 ppm/° C.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a light-transmissive conducting layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has multiple holes to form a photonic crystal structure. The insulating layer is over an upper surface and a sidewall surface of the first platform, and over an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, and the active layer. The light-transmissive conducting layer connects to the photonic crystal structure through an aperture of the insulating layer. The first electrode has an opening corresponding to the aperture. The second electrode is under the substrate.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.