Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: A memory device is provided. The memory device comprises a memory cell, a first power rail and a suppressing circuit. The memory cell is coupled to a word line. The first power rail transmits a first supply voltage. The suppressing circuit comprises a first transistor and a second transistor. The first transistor is diode-connected, coupled to the word line, and disposed at a first layer. The second transistor is diode-connected coupled between the first transistor and the first power rail, and disposed at a second layer under the first layer. The first transistor and the second transistor overlap with each other in a layout view.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: A memory cell includes a first and second transmission pass-gate, a read word line and a write word line. The first transmission pass-gate includes a first and second pass-gate transistor. The second transmission pass-gate includes a third and fourth pass-gate transistor. The read word line is on a first metal layer above a front-side of a substrate. The write word line is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation. The second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: Provided is a method for treating or preventing hair loss or facilitating hair growth or regrowth. More particularly, it relates to a composition for preventing or treating hair loss and/or facilitating hair growth on the scalp and/or skin of a subject in need thereof. The composition includes an effective amount of a polypeptide or a nucleic acid molecule encoding the polypeptide, and the polypeptide comprises an amino acid sequence having an EGF-like domain of thrombomodulin or a conservative variant thereof.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Abstract: A wiring board includes an insulating layer, a wiring layer and a plurality of conductive columns. The insulating layer has a first surface and a second surface opposite to the first surface. The wiring layer is disposed in the insulating layer and has a third surface and a fourth surface opposite to the third surface. The insulating layer covers the third surface, and the second surface of the insulating layer is flush with the fourth surface of the wiring layer. The conductive columns are disposed in the insulating layer and connected to the wiring layer. The conductive columns extend from the third surface of the wiring layer to the first surface of the insulating layer, and protrude from the first surface.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.