Patents by Inventor Chien-cheng Huang

Chien-cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153895
    Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 9, 2024
    Inventors: Harry-HakLay CHUANG, Wei-Cheng WU, Chung-Jen HUANG, Yung Chun TU, Chien Lin LIU, Shun-Kuan LIN, Ping-tzu CHEN
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240128378
    Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Chien-Hua Huang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240116148
    Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 11, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Tike Hoong Phua, Li Yun Chee
  • Publication number: 20240116724
    Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.
    Type: Application
    Filed: July 27, 2023
    Publication date: April 11, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Arya Anil
  • Publication number: 20240094774
    Abstract: A foldable electronic apparatus is provided and includes a base unit and a display unit. The display unit includes a main panel body having a first side and a bottom side substantially perpendicular to each other, and the bottom side is connected to the base unit; a first folding module disposed on the first side; a first side panel body disposed on the first folding module, and the first side panel body is able to transform between a first unfolded state and a first folded state relative to the main panel body with the first folding module as an axis; and a flexible screen disposed on the main panel body, the first folding module and the first side panel body, and the flexible screen includes a first bendable area corresponding to the first folding module.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Applicant: SYNCMOLD ENTERPRISE CORP.
    Inventors: Ching-Hui YEN, Chun-Hao HUANG, Chien-Cheng YEH
  • Publication number: 20240091893
    Abstract: A mounting frame for being mounted with either one of first and second screwdrivers, includes a main frame, a mounting seat, and first and second mounting plates. The mounting seat has a plate attachment hole set. The first mounting plate has a first seat attachment hole set operable to be connected to the plate attachment hole set, and a first driver attachment hole set for the first screwdriver to be attached thereto. The second mounting plate has a second seat attachment hole set operable to be connected to the plate attachment hole set, and a second driver attachment hole set for the second screwdriver to be attached thereto.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 21, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240081005
    Abstract: A flexible screen comprises a multi-layer display structure and a covering structure. The multi-layer display structure includes an outer surface and an inner surface opposite to the outer surface, and the inner surface faces towards the foldable electronic device. The covering structure is disposed on the outer surface of the multi-layer display structure and includes a substrate layer and a plurality of nano-protrusions. The nano-protrusions are formed in array on at least one side of the substrate layer. The flexible screen can transform between an unfolded state and a folded state, and a bending section is partially formed when the flexible screen is in the folded state. The nano-protrusions located in the bending section can release the stress generated in the bending section when the flexible screen transform between the unfolded state and the folded state.
    Type: Application
    Filed: May 30, 2023
    Publication date: March 7, 2024
    Inventors: Chun-Hao HUANG, Ching-Hui YEN, Chien-Cheng YEH
  • Publication number: 20240077804
    Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Hsun LIN, Chien-Cheng CHEN, Shih Ju HUANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20240080382
    Abstract: A foldable electronic device is provided and includes a central base, a torque module, two wing members, two transmission members, two panel bodies, two connecting rods, two drop plates, a synchronous module and a flexible screen. The torque module is disposed on the central base, the wing members pivot relative to the central base, the transmission members are pivotally connected to the torque module and the central base, the panel bodies pivot relative to the wing members and linearly slide relative to the transmission members, the connecting rods pivot relative to the wing members, the drop plates pivot relative to the panel bodies and the connecting rods, the synchronous module drives the transmission members to reverse synchronously, and the flexible screen is arranged on the panel bodies, the drop plates and the wing members and includes a bendable area.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 7, 2024
    Applicant: SYNCMOLD ENTERPRISE CORP.
    Inventors: Chun-Hao Huang, Chien-Cheng Yeh
  • Patent number: 11916146
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11800685
    Abstract: Wireless electronic devices include one or more wireless antennas to provide for wireless communications. The antenna cables are routed internally within the device and typically noise from components located on a circuit board may couple to the antenna cables and cause a degradation in wireless performance, impact antenna sensitivity and cause packet loss. Utilizing raised pathways in a heat sink utilized for thermal transfer of heat to a housing enables tunnels to be formed between the housing and the heat sink. Routing the antenna cables through the tunnels improves noise isolation for the antenna cables while still maintaining the heat transfer. The raised pathways are configured to not interfere with components on the circuit board or components included in the housing. The wireless antennas may be mounted within the housing instead of on the board so no portion of the antenna cables are located on the circuit board.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: October 24, 2023
    Assignee: ARRIS Enterprises LLC
    Inventors: Justin Diep, Chien-Cheng Huang, John Hausman, Hai Lin
  • Patent number: 11788796
    Abstract: A heat conduction device with an inner loop includes a vapor chamber having at least one hole edge and a heat pipe having an outer pipe and an inner pipe. The outer pipe has a closed end and an open end communicating with the hole edge. Two ends of the inner pipe are open. The inner pipe has one end communicating with the vapor chamber through the hole edge and the other end extended along the axial direction of the outer pipe to form at least one port for communicating the closed end of the outer pipe with the inner pipe. The inner pipe is located inside the outer pipe to form a gap annularly. The port communicates with the gap, so that the inner loop is formed between the vapor chamber and the heat pipe.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 17, 2023
    Assignee: NIDEC CHAUN-CHOUNG TECHNOLOGY CORPORATION
    Inventors: Wen-Hsiung Jiang, Chun-An Shen, Chien-Cheng Huang
  • Publication number: 20230047466
    Abstract: A heat conduction device with an inner loop includes a vapor chamber having at least one hole edge and a heat pipe having an outer pipe and an inner pipe. The outer pipe has a closed end and an open end communicating with the hole edge. Two ends of the inner pipe are open. The inner pipe has one end communicating with the vapor chamber through the hole edge and the other end extended along the axial direction of the outer pipe to form at least one port for communicating the closed end of the outer pipe with the inner pipe. The inner pipe is located inside the outer pipe to form a gap annularly. The port communicates with the gap, so that the inner loop is formed between the vapor chamber and the heat pipe.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 16, 2023
    Inventors: Wen-Hsiung JIANG, Chun-An SHEN, Chien-Cheng HUANG
  • Patent number: 11557694
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 17, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
  • Patent number: 11317539
    Abstract: A device includes a hybrid heat sink, and a heat generation component. The hybrid heat sink is attached to the heat generation component. The hybrid heat sink includes a front plate and a rear plate. The front plate is connected to the rear plate by a wall. The front plate includes fins extending away from the front plate and toward the rear plate.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: April 26, 2022
    Assignee: ARRIS ENTERPRISES LLC
    Inventors: Chien-Cheng Huang, Chih-Hao Chien, Xue-Hong Wu
  • Patent number: 11289862
    Abstract: A power module may be attached to and detached from a network extender. The power module may include one or more power connectors that are specific to one or more countries/regions. The power module may include one or more other interfaces (e.g., Ethernet port, etc.). The power module may include a power connector and a male local area network connector on a first surface. The power module may include a local area network port on a second surface, wherein the local area network port is conductively connected to the male local area network connector via a local area network port access.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 29, 2022
    Assignee: ARRIS ENTERPRISES LLC
    Inventors: Paul Joseph Harley, Chien-Cheng Huang, Xue-Hong Wu, John Hausman, Lars Kristoffer Roberg
  • Patent number: D951185
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 10, 2022
    Assignee: ARRIS ENTERPRISES LLC
    Inventors: Paul Joseph Harley, Chien-Cheng Huang, Xue-Hong Wu, John Hausman, Lars Kristoffer Roberg