Abstract: A lighting-dimming device has a dimming module with an encoding function and at least one light module with a decoding function and controlled by the dimming module. The dimming module is designated with a required brightness and address command by a user. A triode AC switch of the dimming module is controlled to chop a power based on the required brightness and address command. The chopped power is transmitted to the light module to control the brightness of the light module. In the chopped power, only a part of cycles of the power is chopped and most of the power waveforms are maintained. Therefore, a high power factor is maintained.

Abstract: A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

Abstract: A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. A default state of the super speed circuit is turning-off. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is used for detecting whether a USB peripheral device is connected to the USB 3.0 host, and controlling turning-on and turning-off of the super speed circuit.

Abstract: A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

Abstract: A phosphor plate includes a glass layer, a wide-angle reflection dichroic filter and a phosphor layer. The wide-angle reflection dichroic filter is disposed on an exit surface of the glass layer. A first blue light and a second blue light of the incident ray are transmissible through the wide-angle reflection dichroic filter. The phosphor layer is disposed beside the wide-angle reflection dichroic filter. By the phosphor layer, the first blue light is excited as a first green light to be outputted and the second blue light is reflected to the wide-angle reflection dichroic filter. The second blue light and a portion of the first green light outputted from the phosphor layer are reflected by the wide-angle reflection dichroic filter, so that the portion of the first green light is transmitted through the phosphor layer and the second blue light is excited as a second green light by the phosphor layer.

Abstract: A method for avoiding unnecessary excessive stay of short cycle in discontinuous reception mechanism begins by using the short cycle while the short cycle timer is running. Then, it determines whether the inactivity timer expires or not and whether the short cycle timer expires or not. If the inactivity timer expires but the short cycle timer does not expire, the short cycle is used. If the short cycle timer expires but the inactivity timer does not expire, the long cycle is used. If the inactivity timer and the short cycle timer expire at the same time, either the short cycle or the long cycle is selected for use.

Abstract: A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding pipeline for enabling the code to be executed without stall so that the number of cycles required to execute the code can be reduced effectively. Moreover, the multiple pipelines can save more cycles when the number of stages in one pipeline is large.

Abstract: A method for avoiding unnecessary excessive stay of short cycle in discontinuous reception mechanism begins by using the short cycle while the short cycle timer is running. Then, it determines whether the inactivity timer expires or not and whether the short cycle timer expires or not. If the inactivity timer expires but the short cycle timer does not expire, the short cycle is used. If the short cycle timer expires but the inactivity timer does not expire, the long cycle is used. If the inactivity timer and the short cycle timer expire at the same time, either the short cycle or the long cycle is selected for use.

Abstract: An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.

Abstract: A central processing unit (CPU) architecture with enhanced branch prediction, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding pipeline for enabling the code to be executed without stall so that the number of cycles required to execute the code can be reduced effectively. Moreover, the multiple pipelines can save more cycles when the number of stages in one pipeline is large.

Abstract: An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.