Patents by Inventor Chien-Chou Chen

Chien-Chou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950687
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 16, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Publication number: 20210074633
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Application
    Filed: November 22, 2020
    Publication date: March 11, 2021
    Inventors: Chien-Chou CHEN, Chun-Hsien CHIEN, Wen-Liang YEH, Wei-Ti LIN
  • Publication number: 20210076508
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 10888001
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 10879167
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 29, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 10863618
    Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 8, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
  • Patent number: 10797017
    Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Po-Chen Lin, Ra-Min Tain, Chun-Hsien Chien, Chien-Chou Chen
  • Publication number: 20200273948
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.
    Type: Application
    Filed: May 15, 2020
    Publication date: August 27, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Patent number: 10700161
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Publication number: 20200194384
    Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
  • Publication number: 20200196440
    Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
  • Publication number: 20200161518
    Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
    Type: Application
    Filed: February 21, 2019
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Yi-Cheng Lin, Yu-Hua Chen, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200163215
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Patent number: 10660202
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200144179
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 7, 2020
    Inventors: Chien-Chou CHEN, Chun-Hsien CHIEN, Wen-Liang YEH, Wei-Ti LIN
  • Publication number: 20200075711
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Application
    Filed: October 15, 2018
    Publication date: March 5, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Publication number: 20190380210
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Application
    Filed: January 10, 2019
    Publication date: December 12, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 10461146
    Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 29, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20190295984
    Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
    Type: Application
    Filed: February 22, 2019
    Publication date: September 26, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Po-Chen Lin, Ra-Min Tain, Chun-Hsien Chien, Chien-Chou Chen
  • Patent number: 10013369
    Abstract: A server system is disclosed. The server system comprises a host system, at least one hard disk (HD) drive, a host bus adapter (HBA), at least one indicator, a storage enclosure processor (SEP), a baseboard management controller (BMC) and a snoop device. The HBA is used to issue a bus signal in a format suitable for transmission over a serial bus according to the received drive state from the at least one HD drive and send the bus signal over the serial bus. The SEP receives the bus signal over the serial bus and drives the at least one indicator to corresponding states. The BMC is coupled to a network. The snoop device detects the bus signal over the serial bus and sends a warning signal to the BMC when a drive failure event is detected.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 3, 2018
    Assignee: Aspeed Technology Inc.
    Inventor: Chien-Chou Chen