Patents by Inventor Chien-Chou Chen
Chien-Chou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250107215Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.Type: ApplicationFiled: September 22, 2023Publication date: March 27, 2025Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chi-Te Lin, Yi-Huan Chen, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong
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Publication number: 20250076846Abstract: The present disclosure describes a system configured to prevent a false low water alarm in a semiconductor processing system. The system includes a liquid reservoir configured to hold a liquid and a sensor system configured to delay an alarm for a predetermined duration of time. In some embodiments, the sensor system includes a sensor configured to determine a level of the fluid in the liquid reservoir and send a signal indicating the level of the fluid to an alarm system and a delay circuit coupled to the fluid level sensor and configured to delay the signal to the alarm system for the predetermined duration of time.Type: ApplicationFiled: September 1, 2023Publication date: March 6, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Shuo CHEN, Hsuan-Yuan Wu, Kai Yuan Chan, Chien Chou Ko
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Publication number: 20250081509Abstract: Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.Type: ApplicationFiled: August 29, 2023Publication date: March 6, 2025Inventors: Jhu-Min Song, Yi-Kai Ciou, Chi-Te Lin, Ying-Chou Chen, Jiou-Kang Lee, Yi-Huan Chen, Chien-Chih Chou, Fei-Yun Chen
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Patent number: 12217732Abstract: An electronic device and a noise cancelation method thereof are provided. The electronic device includes a driver, a driven device, and an inertial measurement device. The driver is configured to generate a driving signal, and generate a noise prediction signal according to the driving signal. The driven device receives the driving signal to execute an operation, wherein the driven device generates a vibration noise according to generated vibrations when executing the operation. The inertial measurement device is configured to sense a position status of the electronic device to generate sensing information. The inertial measurement device receives the noise prediction signal, and compensates the sensing information according to the noise prediction signal to generate compensated sensing information.Type: GrantFiled: June 8, 2023Date of Patent: February 4, 2025Assignee: HTC CorporationInventors: Chao Shuan Huang, Jin-Rong Tsai, Chien Chou Chen, Po-Fei Chen
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Publication number: 20240412718Abstract: An electronic device and a noise cancelation method thereof are provided. The electronic device includes a driver, a driven device, and an inertial measurement device. The driver is configured to generate a driving signal, and generate a noise prediction signal according to the driving signal. The driven device receives the driving signal to execute an operation, wherein the driven device generates a vibration noise according to generated vibrations when executing the operation. The inertial measurement device is configured to sense a position status of the electronic device to generate sensing information. The inertial measurement device receives the noise prediction signal, and compensates the sensing information according to the noise prediction signal to generate compensated sensing information.Type: ApplicationFiled: June 8, 2023Publication date: December 12, 2024Applicant: HTC CorporationInventors: Chao Shuan Huang, Jin-Rong Tsai, Chien Chou Chen, Po-Fei Chen
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Patent number: 12143823Abstract: A method for implementing requests from an app by a SIM in a mobile phone comprises the steps of: binding an app to a BIP server by a mobile phone; delivering a request command to the BIP server from the mobile phone; converting the request command to an APDU format, packing the converted request command in the APDU format in a request packet, and delivering the request packet to an IP of a SIM by the BIP server; receiving and unpacking the request packet to have the converted request command, and providing the converted request command to the SIM; executing the request command to have a result by the SIM; delivering the result in a response packet to the BIP server via the mobile network relayed; unpacking the response packet to fetch the result, and delivering the result to the mobile phone for the app by the BIP server.Type: GrantFiled: May 26, 2022Date of Patent: November 12, 2024Assignee: Taisys Technologies Co., Ltd.Inventors: Chun Hsin Ho, Chih Nung Wang, Chien Chou Chen, Chin Chang Wu
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Publication number: 20230388801Abstract: A method for implementing requests from an app by a SIM in a mobile phone comprises the steps of: binding an app to a BIP server by a mobile phone; delivering a request command to the BIP server from the mobile phone; converting the request command to an APDU format, packing the converted request command in the APDU format in a request packet, and delivering the request packet to an IP of a SIM by the BIP server; receiving and unpacking the request packet to have the converted request command, and providing the converted request command to the SIM; executing the request command to have a result by the SIM; delivering the result in a response packet to the BIP server via the mobile network relayed; unpacking the response packet to fetch the result, and delivering the result to the mobile phone for the app by the BIP server.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: CHUN HSIN HO, CHIH NUNG WANG, CHIEN CHOU CHEN, CHIN CHANG WU
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Patent number: 11678441Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.Type: GrantFiled: November 18, 2020Date of Patent: June 13, 2023Assignee: Unimicron Technology Corp.Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
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Patent number: 11348869Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.Type: GrantFiled: November 22, 2020Date of Patent: May 31, 2022Assignee: Unimicron Technology Corp.Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
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Patent number: 11251350Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.Type: GrantFiled: February 21, 2019Date of Patent: February 15, 2022Assignee: Unimicron Technology Corp.Inventors: Yi-Cheng Lin, Yu-Hua Chen, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
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Patent number: 11201123Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.Type: GrantFiled: November 5, 2019Date of Patent: December 14, 2021Assignee: Unimicron Technology Corp.Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
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Patent number: 10950687Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.Type: GrantFiled: May 15, 2020Date of Patent: March 16, 2021Assignee: Unimicron Technology Corp.Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
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Publication number: 20210074633Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.Type: ApplicationFiled: November 22, 2020Publication date: March 11, 2021Inventors: Chien-Chou CHEN, Chun-Hsien CHIEN, Wen-Liang YEH, Wei-Ti LIN
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Publication number: 20210076508Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Applicant: Unimicron Technology Corp.Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
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Patent number: 10888001Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.Type: GrantFiled: January 10, 2019Date of Patent: January 5, 2021Assignee: Unimicron Technology Corp.Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
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Patent number: 10879167Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.Type: GrantFiled: December 21, 2018Date of Patent: December 29, 2020Assignee: Unimicron Technology Corp.Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
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Patent number: 10863618Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.Type: GrantFiled: February 22, 2019Date of Patent: December 8, 2020Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
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Patent number: 10797017Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.Type: GrantFiled: February 22, 2019Date of Patent: October 6, 2020Assignee: Unimicron Technology Corp.Inventors: Po-Chen Lin, Ra-Min Tain, Chun-Hsien Chien, Chien-Chou Chen
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Publication number: 20200273948Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.Type: ApplicationFiled: May 15, 2020Publication date: August 27, 2020Applicant: Unimicron Technology Corp.Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
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Patent number: 10700161Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.Type: GrantFiled: October 15, 2018Date of Patent: June 30, 2020Assignee: Unimicron Technology Corp.Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin