Patents by Inventor Chien-Chung Wang
Chien-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250133967Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: December 24, 2024Publication date: April 24, 2025Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 12230480Abstract: The present application provides a detaching and installing device for a gas distribution plate of an etching machine, and the etching machine, and relates to the field of semiconductor manufacturing technologies, aiming at addressing the problems that it is quite difficult to detach and install the gas distribution plate of the etching machine and that the gas distribution plate is highly likely to be polluted. The detaching and installing device for the gas distribution plate of the etching machine includes a gripping member, a connecting member and a fixing member, the fixing member is detachably connected to the gas distribution plate of the etching machine, and the gripping member and the fixing member are connected through the connecting member; the gripping member is provided thereon with a gripping portion for grip by a user hand.Type: GrantFiled: October 22, 2021Date of Patent: February 18, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Ko Wei Chen, Li Meng, Chien Chung Wang
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Publication number: 20250041975Abstract: A laser slicing apparatus, in which a laser module provides a laser beam, and a light splitting element of a focusing lens set splits the laser beam into a plurality of focused laser beams to form a plurality of induce lines having first laser modified cracks in a modified layer at a predetermined depth inside a substrate. A rotating module rotates the light splitting element with an angle, and the light splitting element converts the focused laser beams according to this angle to form a plurality of modified groups between the induce lines. Each modified group includes a plurality of modified lines having second laser modified cracks, and the first laser modified cracks and the second laser modified cracks are connected to each other to form a continuous laser modified crack in the modified layer at the predetermined depth inside the substrate, thereby speeding up the laser slicing production.Type: ApplicationFiled: September 11, 2023Publication date: February 6, 2025Applicant: Industrial Technology Research InstituteInventors: Jyun-Jhih WANG, Chun-Ming CHEN, Yu-Chung LIN, Pin-Hao HU, Chien-Jung HUANG
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Patent number: 12219879Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: GrantFiled: November 28, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20250028151Abstract: An optical element driving mechanism is provided, including a fixed part, a movable part, a metallic member and a driving assembly. The fixed part includes a base. The movable part is movably connected to the fixed part, and carries an optical element, the optical element has an optical axis. The metallic member is disposed on the base, and includes an inner electrical connection part and an outer electrical connection part, the inner electrical connection part and the outer electrical connection part are connected to each other. The driving assembly includes at least one driving magnetic element and drives the movable part to move relative to the fixed part.Type: ApplicationFiled: October 9, 2024Publication date: January 23, 2025Inventors: Chien-Lun HUANG, Shao-Chung CHANG, Wei-Cheng WANG, Che-Hsiang CHIU, Fu-Yuan WU, Shou-Jen LIU
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Publication number: 20250014824Abstract: A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.Type: ApplicationFiled: September 19, 2024Publication date: January 9, 2025Inventors: Chien-Chung WANG, Hsih-Yang CHIU
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Patent number: 12125642Abstract: A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer.Type: GrantFiled: March 31, 2023Date of Patent: October 22, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chien-Chung Wang, Hsih-Yang Chiu
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Patent number: 12113046Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: GrantFiled: November 2, 2023Date of Patent: October 8, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
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Publication number: 20240258220Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.Type: ApplicationFiled: April 10, 2024Publication date: August 1, 2024Inventors: Chien-Chung WANG, Hsih-Yang CHIU
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Publication number: 20240222950Abstract: A retractable cable device includes a shell, a cable disposed in the shell, a pulley disposed in the shell, a spring assembly disposed in the shell, and a cover covered to the shell. The shell has a bottom board. Two sides of an inner surface of the bottom board extend upward to form two first slide rails. The cable is mounted around the pulley. Two sides of a top surface and two sides of a bottom surface of the pulley are recessed inward to form a plurality of locating grooves. The locating grooves of the bottom surface of the pulley guide the first slide rails of the shell. Two sides of a bottom surface of the cover extend downward to form two second slide rails. The locating grooves of the top surface of the pulley guide the second slide rails of the cover.Type: ApplicationFiled: October 4, 2023Publication date: July 4, 2024Inventors: KUANG-MO CHIEN, CHIEN-CHUNG WANG
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Patent number: 12013798Abstract: A method of data synchronization is to be implemented by a redundant server system including an active input/output module (IOM) and a passive IOM. The method includes: allocating a primary transfer buffer in the active IOM; allocating a secondary transfer buffer in the passive IOM; collecting pieces of secondary dedicated-sensor data, and storing the pieces of secondary dedicated-sensor data in the primary transfer buffer at once; collecting pieces of primary dedicated-sensor data; after the pieces of primary dedicated-sensor data have been collected, updating the primary state data based on the pieces of primary dedicated-sensor data thus collected and the pieces of secondary dedicated-sensor data stored in the primary transfer buffer at once, and storing the primary state data thus updated in the secondary transfer buffer; and updating the secondary state data based on the primary state data that have been updated and that are stored in the secondary transfer buffer.Type: GrantFiled: November 3, 2022Date of Patent: June 18, 2024Assignee: Mitac Computing Technology CorporationInventors: Chin-Hung Tan, Heng-Chia Hsu, Chien-Chung Wang, Yu-Shu Yeh, Chen-Yin Lin
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Patent number: 11984389Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.Type: GrantFiled: April 23, 2023Date of Patent: May 14, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chien-Chung Wang, Hsih-Yang Chiu
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Patent number: 11915952Abstract: The present application provides a temperature control method, an apparatus, an electronic device and a storage medium for an etching workbench. A real-time temperature of an etching workbench and a real-time temperature of a temperature control fluid are acquired firstly; then, a temperature control instruction is determined according to the real-time temperature of the etching workbench, the real-time temperature of the temperature control fluid and a limit temperature; and finally, in response to the temperature control instruction, a target operating temperature of the etching workbench is stabilized within a preset range by a circulating temperature control fluid loop.Type: GrantFiled: June 7, 2021Date of Patent: February 27, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yong Fang, Chien Chung Wang
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Publication number: 20240063175Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: WEI-ZHONG LI, YI-TING SHIH, CHIEN-CHUNG WANG, HSIH-YANG CHIU
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Patent number: 11899419Abstract: An integrated control management system includes an input output device. The input output device includes a database, a memory module, a first processing module, and a second processing module. The memory module receives and stores a plurality of integrated control commands, and one of the integrated control commands is generated based on a hardware control command for setting a hardware control transmitted by another input and output device. The first processing module reads the integrated control command from the memory module and obtains the hardware control data from the integrated control command. The first processing module updates the hardware control data to the database. The second processing module reads the database and updates the hardware control data stored in the database to another database in another input output device. The second processing module sets the hardware control based on the hardware control data stored in the database.Type: GrantFiled: November 11, 2021Date of Patent: February 13, 2024Assignee: MITAC COMPUTING TECHNOLOGY CORPORATIONInventors: Heng-Chia Hsu, Chen-Yin Lin, Yu-Shu Yeh, Chien-Chung Wang, Chin-Hung Tan
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Patent number: 11876072Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: GrantFiled: September 2, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
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Patent number: 11847467Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.Type: GrantFiled: June 29, 2022Date of Patent: December 19, 2023Assignee: MITAC COMPUTING TECHNOLOGY CORPORATIONInventors: Yu-Shu Yeh, Heng-Chia Hsu, Chen-Yin Lin, Chien-Chung Wang, Chin-Hung Tan
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Publication number: 20230307374Abstract: An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.Type: ApplicationFiled: August 12, 2022Publication date: September 28, 2023Inventors: Kuo-Chiang Ting, Tu-Hao Yu, Shun-Jang Laio, Chien-Chung Wang, Chia-Ching Lin
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Publication number: 20230268258Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.Type: ApplicationFiled: April 23, 2023Publication date: August 24, 2023Inventors: Chien-Chung WANG, Hsih-Yang CHIU
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Publication number: 20230245826Abstract: A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer.Type: ApplicationFiled: March 31, 2023Publication date: August 3, 2023Inventors: Chien-Chung WANG, Hsih-Yang CHIU