Patents by Inventor Chien-Chung Wang

Chien-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160141390
    Abstract: A method for manufacturing display panel is disclosed, which comprises: (A) providing a substrate, an oxide semiconductor layer disposed on the substrate, and a gate electrode disposed on the substrate and corresponding to the oxide semiconductor layer; (B) forming a metal layer on the oxide semiconductor layer; (C) forming a photoresist on the metal layer, and etching the metal layer to form a source electrode and a drain electrode; (D) heating the photoresist and the photoresist covers at least partial of side walls of the source electrode and the drain electrode; (E) applying an alkaline solution on the substrate; and (F) removing the photoresist to expose the source electrode and the drain electrode.
    Type: Application
    Filed: October 27, 2015
    Publication date: May 19, 2016
    Inventors: Ker-Yih KAO, Chin-Lung TING, Jung-Fang CHANG, Chien-Chung WANG
  • Patent number: 9219110
    Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chung Wang, Wei-Min Tseng, Shih-Guo Shen, Huey-Chi Chu, Wen-Chuan Chiang
  • Publication number: 20150295020
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Tseng, Shih-Guo Shen, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
  • Publication number: 20150295019
    Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chung Wang, Wei-Min Tseng, Shih-Guo Shen, Huey-Chi Chu, Wen-Chuan Chiang
  • Publication number: 20150294936
    Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Guo Shen, Wei-Min Tseng, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
  • Publication number: 20090119281
    Abstract: The application borrows terminology from data mining, association rule learning and topology. A geometric structure represents a collection of concepts in a document set. The geometric structure has a high-frequency keyword set that co-occurs closely which represents a concept in a document set. Document analysis seeks to automate the understanding of knowledge representing the author's idea. Granular computing theory deals with rough sets and fuzzy sets. One of the key insights of rough set research is that selection of different sets of features or variables will yield different concept granulations. Here, as in elementary rough set theory, by “concept” we mean a set of entities that are indistinguishable or indiscernible to the observer (i.e., a simple concept), or a set of entities that is composed from such simple concepts (i.e., a complex concept).
    Type: Application
    Filed: November 29, 2007
    Publication date: May 7, 2009
    Inventors: Andrew Chien-Chung Wang, Tsau Young Lin, I-Jen Chiang
  • Publication number: 20090008521
    Abstract: A clamping device for a webcam according to the present invention comprising a first arm having an extending base bearing the webcam, with a guide rail mounted at each lateral side of the base, between which the first slots are mounted for connecting purposes; a second arm having a pair of first shafts; and a connecting member having a pair of sliding tracks corresponding to the guide rails of the first arm, a pair of second shafts corresponding to the first slots with connecting purposes, and a pair of second slots with connecting purposes corresponding to the first shafts of the second arm invention comprising a first arm having an extending base bearing the webcam, with a guide rail mounted at each lateral side of the base, between which the first slots are mounted for connecting purposes; a second arm having a pair of first shafts; and a connecting member having a pair of sliding tracks corresponding to the guide rails of the first arm, a pair of second shafts corresponding to the first slots with connect
    Type: Application
    Filed: March 11, 2008
    Publication date: January 8, 2009
    Applicant: CHICONY ELECTRONICS CO. LTD
    Inventors: Peng-Yuan Lee, Chien-Chung Wang
  • Patent number: 7377143
    Abstract: A door lock able to be prevented from being locked by an unexpected exterior force includes a main body, a fixing member and a handle. The main body is provided with a sleeve at the center extended outwards from two sides. One end of the sleeve is matched with a lining tube that is linked with a button. Via rotating the button for an angle, projections of a stopper attached with one end of the button is to be guided into a blocking groove of the lining tube, enabling the button to be locked in the blocking groove so that the button can not be pressed down, able to prevent the button from being locked by an unexpected exterior force.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: May 27, 2008
    Inventor: Chien-chung Wang
  • Publication number: 20070180874
    Abstract: A door lock able to be prevented from being locked by an unexpected exterior force includes a main body, a fixing member and a handle. The main body is provided with a sleeve at the center extended outwards from two sides. One end of the sleeve is matched with a lining tube that is linked with a button. Via rotating the button for an angle, projections of a stopper attached with one end of the button is to be guided into a blocking groove of the lining tube, enabling the button to be locked in the blocking groove so that the button can not be pressed down, able to prevent the button from being locked by an unexpected exterior force.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 9, 2007
    Inventor: Chien-chung Wang
  • Patent number: 6841460
    Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: January 11, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung, Yuan-Chang Huang
  • Publication number: 20040238656
    Abstract: A fragrant pouch which includes an inner bag made of one-way permeable film containing liquid fragrant essence oil or perfume; an outer bag made of non-woven fabric with both bags laminated together by fusion or by high frequency into various types of form as desired; an opening to the pouch, and a hook to the opening; that can be placed flat in drawer and shoes or hung up in car, closet and closet for the fragrant essence oil or perfume to seep out of the inner bag through the non-woven outer bag for slow volatilization and emission into the ambient space.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventor: Chien-Chung Wang
  • Publication number: 20040171207
    Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.
    Type: Application
    Filed: March 12, 2004
    Publication date: September 2, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Shu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung, Yuan-Chang Huang
  • Patent number: 6734085
    Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung, Yuan-Chang Huang
  • Patent number: D556133
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: November 27, 2007
    Assignee: Advanced Connectek inc
    Inventor: Chien Chung Wang
  • Patent number: D557213
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: December 11, 2007
    Assignee: Advanced Connectek Inc.
    Inventor: Chien Chung Wang