Patents by Inventor Chien-Fan Chen

Chien-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296388
    Abstract: Provided herein is a battery cell of a battery pack to power an electric vehicle. The battery cell can include a housing having a first end and a second end and defining an inner region. The battery cell can include a lid that includes a first polarity portion, a second polarity portion and a first isolation layer between the first polarity portion and the second polarity portion. The second polarity portion can be coupled with the first end of the housing. The battery cell can include an electrolyte disposed in the inner region defined by the housing and a first polarity tab that electrically couples the electrolyte with the first polarity portion of the lid. The first polarity tab can include a spring element. The spring element can be configured to apply a force at a predetermined level to the electrolyte.
    Type: Application
    Filed: October 5, 2018
    Publication date: September 26, 2019
    Inventors: Chien-Fan Chen, Ying Liu
  • Publication number: 20190296405
    Abstract: Provided herein are battery cells for battery packs in electric vehicles. The battery cell can include a housing having a first end, a second end, and an inner surface. The housing can define an inner region and an electrolyte can be disposed in the inner region of the housing. A gasket can couple a lid with the first end of the housing to seal the battery cell. The inner surface can include a recess and a groove. The groove can form a path from the recess to an egress point on the first end of the housing. A pressure sensor can be disposed in the recess. The pressure sensor can couple with a pressure sensor wire disposed in the groove and the pressure sensor wire can extend from the recess and past the egress point on the first end of the housing to provide sensed pressure information.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 26, 2019
    Inventors: Yifan Tang, Chien-Fan Chen, Ying Liu
  • Publication number: 20190296282
    Abstract: Provided herein are battery packs for electric vehicles. A battery pack can include a housing having cavities. The battery pack can include electrode structures having a first tab terminal and a second tab terminal. A cover can be disposed over the housing. The cover can include first junction connectors extending between a first surface of the cover and a second surface of the cover. The first tab terminal of each electrode structure can be welded to respective first junction connectors.
    Type: Application
    Filed: June 14, 2018
    Publication date: September 26, 2019
    Inventors: Ying Liu, Derek Nathan Wong, Chien-Fan Chen, Yifan Tang
  • Publication number: 20190296297
    Abstract: A battery cell of a battery pack to power an electric vehicle can include a housing to at least partially enclose an electrode assembly is provided. The battery cell can include a vent plate coupled with the housing via a glass weld at a lateral end of the battery cell. The vent plate can include a scoring pattern to cause the vent plate to rupture in response to a threshold pressure. A first end of a polymer tab can be electrically coupled with the vent plate at an area within a scored region defined by the scoring pattern. A second end of the polymer tab can be electrically coupled with an electrode assembly. The polymer tab can melt in response to either a threshold temperature or a threshold current within the battery cell.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 26, 2019
    Inventors: Ying Liu, Scott Quinlan Freeman Monismith, Chien-Fan Chen, Jeremy Andrew Elsberry, Yifan Tang
  • Publication number: 20190296283
    Abstract: Provided herein are battery cell modules of battery packs to power electric vehicles. The battery cell modules can include a plurality of battery cells, each of which can include a housing having a first end and a second end, the housing defining an inner region. An electrode structure can be disposed in the inner region defined by the housing, the electrode structure including a cathode tab that extends from the first end of the housing, and an anode tab that extends from the first end of the housing. A lid can be coupled with the first end of the housing, the lid including a cathode tab opening and an anode tab opening. A base includes a plurality cathode sockets receiving respective cathode tabs of the plurality of battery cells and a plurality of anode sockets receiving respective anode tabs of the plurality of battery cells.
    Type: Application
    Filed: October 5, 2018
    Publication date: September 26, 2019
    Inventors: Chien-Fan Chen, Ying Liu
  • Publication number: 20190296285
    Abstract: Provided herein are battery cell modules of battery packs to power electric vehicles. The battery cell modules can include a plurality of battery cells, each of which can include a housing having a first end and a second end, the housing defining an inner region. An electrode structure can be disposed in the inner region defined by the housing, the electrode structure including a cathode tab that extends from the first end of the housing, and an anode tab that extends from the first end of the housing. A lid can be coupled with the first end of the housing, the lid including a cathode tab opening and an anode tab opening. A base includes a plurality cathode sockets receiving respective cathode tabs of the plurality of battery cells and a plurality of anode sockets receiving respective anode tabs of the plurality of battery cells.
    Type: Application
    Filed: December 26, 2018
    Publication date: September 26, 2019
    Inventors: Chien-Fan Chen, Ying Liu
  • Patent number: 10424769
    Abstract: Provided herein are battery packs for electric vehicles. A battery pack can include a housing having cavities. The battery pack can include electrode structures having a first tab terminal and a second tab terminal. A cover can be disposed over the housing. The cover can include first junction connectors extending between a first surface of the cover and a second surface of the cover. The first tab terminal of each electrode structure can be welded to respective first junction connectors.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 24, 2019
    Assignees: CHONGQING JINKANG NEW ENERGY VEHICLE CO., LTD., SF MOTORS, INC.
    Inventors: Ying Liu, Derek Nathan Wong, Chien-Fan Chen, Yifan Tang
  • Publication number: 20180248221
    Abstract: A system for a high temperature, high energy density secondary battery that includes an electrolyte comprising an ionic liquid solvent, and electrolyte salts; a metallic anode; a cathode, compatible with the electrolyte and comprising an active material and a polyimide binder; and a separator component that separates the cathode and anode.
    Type: Application
    Filed: February 24, 2018
    Publication date: August 30, 2018
    Inventors: Richard Y. Wang, Mauro Pasta, Olivia Risset, Chien-Fan Chen
  • Patent number: 9768139
    Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 19, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wan-Ting Chiu, Chien-Fan Chen
  • Patent number: 9741675
    Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 22, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Dao-Long Chen, Ping-Feng Yang, Chang-Chi Lee, Chien-Fan Chen
  • Publication number: 20170040279
    Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 9, 2017
    Inventors: Wan-Ting CHIU, Chien-Fan CHEN
  • Patent number: 9508671
    Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element and two pillar structures. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on the one bonding pad. The two pillar structures are symmetric and formed of a same material.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: November 29, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wan-Ting Chiu, Chien-Fan Chen
  • Publication number: 20160307864
    Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element and two pillar structures. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on the one bonding pad.
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Inventors: Wan-Ting CHIU, Chien-Fan CHEN
  • Publication number: 20160211235
    Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.
    Type: Application
    Filed: January 16, 2015
    Publication date: July 21, 2016
    Inventors: Dao-Long CHEN, Ping-Feng YANG, Chang-Chi LEE, Chien-Fan CHEN
  • Patent number: 8552553
    Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jian-Wen Lo, Chien-Fan Chen
  • Patent number: 8334594
    Abstract: The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: December 18, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jian-Wen Lo, Chien-Fan Chen
  • Publication number: 20110084389
    Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0.
    Type: Application
    Filed: May 28, 2010
    Publication date: April 14, 2011
    Inventors: Jian-Wen Lo, Chien-Fan Chen
  • Publication number: 20110084381
    Abstract: The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.
    Type: Application
    Filed: August 13, 2010
    Publication date: April 14, 2011
    Inventors: Jian-Wen Lo, Chien-Fan Chen
  • Patent number: 7671141
    Abstract: Disclosed herein are second order nonlinear optic polyimide polymers comprising repeating units represented by the formula: wherein each of the substituents is given the definition as set forth in the Specification and Claims. Also disclosed are the preparation processes of these polymers, chromophore-forming compounds for synthesis of these polymers, and the intermediate polymers thereof. The second order nonlinear optic polyimide polymers of formula (I) may be used in the manufacture of electro-optic (EO) devices, such as electro-optic waveguide devices.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 2, 2010
    Assignee: National Sun Yat-Sen University
    Inventors: Tzu-Chien Hsu, Chien-Fan Chen, Shou-Shiun Wu
  • Patent number: 7670512
    Abstract: Disclosed herein are second order nonlinear optic polyimide polymers comprising repeating units represented by the formula: wherein each of the substituents is given the definition as set forth in the Specification and Claims. Also disclosed are the preparation processes of these polymers, chromophore-forming compounds for synthesis of these polymers, and the intermediate polymers thereof. The second order nonlinear optic polyimide polymers of formula (I) may be used in the manufacture of electro-optic (EO) devices, such as electro-optic waveguide devices.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 2, 2010
    Assignee: National Sun Yat-Sen University
    Inventors: Tzu-Chien Hsu, Chien-Fan Chen, Shou-Shiun Wu