Patents by Inventor Chien-Fan Chen

Chien-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12264102
    Abstract: A method for producing photocatalytic mortar includes providing a mortar-producing material including a fine aggregate and cement, a reactant mixture including a zinc source and urea, and a microorganism-containing mixture including water and a urease-producing microorganism, subjecting the microorganism-containing mixture and the reactant mixture to microbial induced precipitation in the mortar-producing material, subjecting zinc carbonate crystal-containing mortar produced to curing for the same to undergo hydration, and subjecting cured mortar to hydrothermal synthesis, so that zinc carbonate crystals therein are converted to nano zinc oxide crystals.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 1, 2025
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Chien-Yen Chen, Yi-Hsun Huang, Pin-Yun Lin, Wei-Fan Ye
  • Patent number: 12267961
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Publication number: 20250055102
    Abstract: An apparatus for smart packaging and inventory control is provided herein and comprises a housing comprising a lid configured to be opened and closed to allow a battery to be loaded and unloaded to and from the housing and a controller configured to monitor at least one of a battery state of health or a battery state of charge when the battery is disposed in the housing and display the state of health or the state of charge of the battery via an indicator on the housing.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 13, 2025
    Inventors: Jonathan List EHLMANN, Conner O’Grady FEAR, Chien-Fan CHEN
  • Publication number: 20240164021
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Chien-Hao WANG
  • Patent number: 11923285
    Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Jen Cheng, Chien-Fan Chen
  • Patent number: 11882660
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: January 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Publication number: 20230327446
    Abstract: The present disclosure provides an energy storage system. For example, an energy storage system comprises a chassis and a printed circuit board assembly connected to the chassis and comprising a connecting/disconnecting device configured to connect to a corresponding connecting/disconnecting device on the battery cell for enabling connection of the battery cell to the chassis.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Wei JIANG, Chien-Fan CHEN, Christopher McNair LYKE, Chris Morrow YOUNG
  • Patent number: 11587881
    Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Yu-Ju Liao, Chu-Jie Yang, Sheng-Hung Shih
  • Patent number: 11553596
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Publication number: 20220278052
    Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.
    Type: Application
    Filed: May 17, 2022
    Publication date: September 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Yu-Ju LIAO
  • Publication number: 20220216136
    Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Jen CHENG, Chien-Fan CHEN
  • Patent number: 11335646
    Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Yu-Ju Liao
  • Patent number: 11296030
    Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
  • Patent number: 11277917
    Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang, I-Chia Lin
  • Patent number: 11228071
    Abstract: A battery cell of a battery pack to power an electric vehicle can include a housing to at least partially enclose an electrode assembly is provided. The battery cell can include a vent plate coupled with the housing via a glass weld at a lateral end of the battery cell. The vent plate can include a scoring pattern to cause the vent plate to rupture in response to a threshold pressure. A first end of a polymer tab can be electrically coupled with the vent plate at an area within a scored region defined by the scoring pattern. A second end of the polymer tab can be electrically coupled with an electrode assembly. The polymer tab can melt in response to either a threshold temperature or a threshold current within the battery cell.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: January 18, 2022
    Assignees: CHONGQING JINKANG NEW ENERGY VEHICLE CO., LTD., SF MOTORS, INC.
    Inventors: Ying Liu, Scott Quinlan Freeman Monismith, Chien-Fan Chen, Jeremy Andrew Elsberry, Yifan Tang
  • Patent number: 11139179
    Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Yu-Ju Liao
  • Publication number: 20210298176
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Chien-Hao WANG
  • Publication number: 20210287997
    Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Yu-Ju LIAO
  • Publication number: 20210280521
    Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Yu-Ju LIAO, Chu-Jie YANG, Sheng-Hung SHIH
  • Patent number: 11032911
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 8, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang