Patents by Inventor Chien Hsun Huang

Chien Hsun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 10802398
    Abstract: The direct patterning method includes: providing a substrate having a display area and a peripheral area, which a peripheral circuit having a bonding pad is disposed on the peripheral area; sequentially disposing a metal nanowire layer, a pre-cured film layer and a negative-type photosensitive layer thereon; performing a photolithography step; and curing the pre-cured film layer. The photolithography step includes exposing the negative-type photosensitive layer to define a removal region and a reserved region; and removing the negative-type photosensitive layer, the pre-cured film layer and the metal nanowire layer in the removal region by using a developer, such that a touch sensing electrode is fabricated in the display area and the bonding pad is exposed.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 13, 2020
    Assignee: TPK TOUCH SOLUTIONS INC.
    Inventors: Chao-Sung Li, Ho-Hsun Chi, Fang Fang, Zheng-Pang Huang, Chien-Hsien Yu, Chih-Min Chen, Shan-Yu Wu
  • Publication number: 20200258891
    Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.
    Type: Application
    Filed: March 11, 2019
    Publication date: August 13, 2020
    Inventors: Chien-Hui Huang, Tsung-Hsun Wu, Po-Lin Chen
  • Patent number: 10741513
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200235079
    Abstract: A chip-scale LED package structure includes a white light emitting unit for emitting a white light, a red flip-chip LED for emitting a red light, a green flip-chip LED for emitting a green light, a blue flip-chip LED for emitting a blue light, and an encapsulation layer. The encapsulation includes an encapsulation resin and a plurality of refractive particles distributed in the encapsulation resin. The encapsulation layer encapsulates the white light emitting unit, the red flip-chip LED, the green flip-chip LED, and the blue flip-chip LED. Moreover, electrodes of the white light emitting unit, electrodes of the red flip-chip LED, electrodes of the green flip-chip LED, and electrodes of the blue flip-chip LED are exposed from the encapsulation layer.
    Type: Application
    Filed: December 18, 2019
    Publication date: July 23, 2020
    Inventors: TIEN-YU LEE, CHIH-YUAN CHEN, WEI-LUN TSAI, CHIEN-TUNG HUANG, WEI-HSUN HSU, WEI-CHIEN HUNG
  • Patent number: 10573649
    Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Publication number: 20190271912
    Abstract: The direct patterning method includes: providing a substrate having a display area and a peripheral area, which a peripheral circuit having a bonding pad is disposed on the peripheral area; sequentially disposing a metal nanowire layer, a pre-cured film layer and a negative-type photosensitive layer thereon; performing a photolithography step; and curing the pre-cured film layer. The photolithography step includes exposing the negative-type photosensitive layer to define a removal region and a reserved region; and removing the negative-type photosensitive layer, the pre-cured film layer and the metal nanowire layer in the removal region by using a developer, such that a touch sensing electrode is fabricated in the display area and the bonding pad is exposed.
    Type: Application
    Filed: February 27, 2019
    Publication date: September 5, 2019
    Inventors: Chao-Sung Li, Ho-Hsun Chi, Fang Fang, Zheng-Pang Huang, Chien-Hsien Yu, Chih-Min Chen, Shan-Yu Wu
  • Patent number: 10356296
    Abstract: An image capture apparatus including a light guide device, a transparent device, a light source and an image capture device is provided. The light guide device includes a top surface, a bottom surface opposite to the top surface, a light incident surface connected between the top surface and the bottom surface and a light emitting surface opposite to the top surface. The bottom surface is connected between the light incident surface and the light emitting surface. An acute angle ? is included between the light incident surface and the top surface. The transparent device is disposed on the top surface of the light guide device. The light source is used to emit a light beam. The image capture device is disposed on the light emitting surface of the light guide device.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Gingy Technology Inc.
    Inventors: Chien-Hsing Wu, Cheng-Jyun Huang, Po-Hsun Shen
  • Patent number: 10345254
    Abstract: Detection methods for an electroplating process are provided. A detection method includes immersing a substrate into an electrolyte solution to perform an electroplating process. The electrolyte solution includes an additive agent. The detection method also includes immersing a detection device into the electrolyte solution. The detection method further includes applying a first alternating current (AC) voltage or direct current (DC) voltage to the detection device to detect the concentration of the additive agent. In addition, the detection method includes applying a combination of a second AC voltage and a second DC voltage to the detection device to inspect the electrolyte solution. An impurity is detected in the electrolyte solution. The detection method also includes replacing the electrolyte solution containing the impurity with another electrolyte solution.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chang Huang, Jui-Mu Cho, Chien-Hsun Pan, Chun-Chih Lin
  • Publication number: 20190189577
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 20, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 10325994
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 10312384
    Abstract: A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Cheng Lin, Chien-Kai Peng, Chen-Cheng Lin, Chen-Hsun Du, Chorng-Jye Huang, Chun-Ming Yeh
  • Patent number: 10148050
    Abstract: A cable connector assembly including: a first electrical connector comprising a frontal first mating member for inputting a first voltage, a first voltage point for outputting the first voltage, and a second voltage point for outputting a second voltage different from the first voltage; a second electrical connector comprising a frontal second mating member and a second printed circuit board, the second mating member comprising a power contact; and a cable connecting the first electrical connector and the second electrical connector electrically, the cable comprising a first wire and a second wire, the first wire connecting the first voltage point and the power contact electrically, the second wire connecting the second voltage point and the second printed circuit board electrically.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 4, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Guang-Yu Ma, Dou-Feng Wu, Xiao-Li Li, Chien-Hsun Huang
  • Patent number: 10116101
    Abstract: A cable connector assembly includes: a mating unit; a cable; a printed circuit board (PCB) interconnected between the mating unit and the cable; a protective cover and a thermistor affixed to the protective cover, the protective cover and the thermistor being mounted on the PCB; a metal shell enclosing the PCB, a rear of the mating unit, and a front of the cable; an insulative inner cover over-molding the PCB, the metal shell, the rear of the mating unit, and the front of the cable; and an insulative outer cover over-molding the insulative inner cover. A method of making the cable connector assembly includes affixing the thermistor to the protective cover and mounting the protective cover and the thermistor on the PCB.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: October 30, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chien-Hsun Huang, Xiao-Li Li, Dou-Feng Wu
  • Patent number: 10079448
    Abstract: A cable connector assembly includes a first connector having a mating portion and a rear portion; a cable connected with the first connector; and a seizing structure bundling the cable. The seizing structure includes a metal wire wrapping the cable, a middle insulative layer cladding the metal wire, and an outer insulative layer wrapping the middle insulative layer.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 18, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Wen-Feng Lv, Dou-Feng Wu, Xiao-Li Li, Chien-Hsun Huang
  • Patent number: 10027069
    Abstract: A cable connector assembly includes: a mating unit; a cable; a printed circuit board (PCB) interconnected between the mating unit and the cable, the PCB carrying a thermistor; a protective cover mounted on the PCB and enclosing the thermistor; a metal shell enclosing the PCB, a rear of the mating unit, and a front of the cable; an insulative inner cover over-molding the PCB, the metal shell, the rear of the mating unit, and the front of the cable; and an insulative outer cover over-molding the inner cover.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 17, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chien-Hsun Huang, Dou-Feng Wu, Shuo Liu, Xiao-Li Li
  • Publication number: 20180191107
    Abstract: A cable connector assembly includes: a mating unit; a cable; a printed circuit board (PCB) interconnected between the mating unit and the cable; a protective cover and a thermistor affixed to the protective cover, the protective cover and the thermistor being mounted on the PCB; a metal shell enclosing the PCB, a rear of the mating unit, and a front of the cable; an insulative inner cover over-molding the PCB, the metal shell, the rear of the mating unit, and the front of the cable; and an insulative outer cover over-molding the insulative inner cover. A method of making the cable connector assembly includes affixing the thermistor to the protective cover and mounting the protective cover and the thermistor on the PCB.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 5, 2018
    Inventors: CHIEN-HSUN HUANG, XIAO-LI LI, DOU-FENG WU
  • Patent number: 10006094
    Abstract: Degenerate primers for amplifying fragments of the nucleotide sequences of mutL and dnaJ genes of a lactic acid bacterium of Lactobacillus casei group are provided. Methods and kits for discriminating interspecies and intraspecies of a lactic acid bacteria of Lb. casei group are also provided.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 26, 2018
    Assignee: Food Industry Research And Development Institute
    Inventors: Chien-Hsun Huang, Li-Na Huang, Li-Ting Wang
  • Publication number: 20180138643
    Abstract: A cable connector assembly includes: a mating unit; a cable; a printed circuit board (PCB) interconnected between the mating unit and the cable, the PCB carrying a thermistor; a protective cover mounted on the PCB and enclosing the thermistor; a metal shell enclosing the PCB, a rear of the mating unit, and a front of the cable; an insulative inner cover over-molding the PCB, the metal shell, the rear of the mating unit, and the front of the cable; and an insulative outer cover over-molding the inner cover.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 17, 2018
    Inventors: CHIEN-HSUN HUANG, DOU-FENG WU, SHUO LIU, XIAO-LI LI