Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.

Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A package structure including a first semiconductor die, at least one second semiconductor die conductive terminals and an insulating encapsulation is provided. The at least one second semiconductor die is stacked on and electrically connected to the first semiconductor die. The conductive terminals are disposed on and electrically connected to the first semiconductor die. The insulating encapsulation laterally encapsulates the first semiconductor die, the at least one second semiconductor die and the conductive terminals, wherein the conductive terminals protrude from a surface of the insulating encapsulation. Furthermore, a method for forming the above-mentioned is also provided.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 ?m to 30 ?m; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A package structure includes a substrate component, a redistribution structure, a package structure, and a probe head. The substrate component is laterally covered by an insulating encapsulation. The redistribution structure is disposed over the substrate component and the insulating encapsulation and electrically connected with the substrate component at a first side, wherein the redistribution structure comprises: a dielectric layer at a second side opposite to the first side; at least one conductive pad disposed in the dielectric layer, wherein a portion of the at least one conductive pad is exposed by the dielectric layer; and at least one conductive pattern in contact with the portion of the at least one conductive pad, wherein a hardness of the at least one conductive pattern is greater than a hardness of the at least one conductive pad. The probe head is electrically connected with the at least one conductive pattern and the at least one conductive pad.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, a conductive pillar and a solder material is provided. The redistribution circuit structure has a first surface and a second surface opposite to the first surface and includes a first insulating layer and a first redistribution pattern in the insulating layer. The first redistribution pattern comprises a first contact pad disposed at the first surface. The wiring substrate is disposed opposite the first surface of the redistribution circuit structure and includes a second insulating layer and a second redistribution pattern in the second insulating layer. The second redistribution pattern comprises a second contact pad. The conductive pillar is disposed between the first contact pad and the second contact pad. The solder material disposed between the conductive pillar and the second contact pad.

Abstract: A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.

Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.

Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

Abstract: Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.