Patents by Inventor Chien-Hsun Lee

Chien-Hsun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE
    Publication number: 20210057331
    Abstract: A semiconductor package includes a semiconductor die encapsulated by an insulating encapsulation, a redistribution circuit structure disposed over the semiconductor die and the insulating encapsulation, the redistribution circuit structure being electrically connected to the semiconductor die; and a conductive feature having a first portion embedded in the redistribution circuit structure and a second portion connected to the first portion, the first portion having a first long axis and a first short axis perpendicular to the long axis in a top view, the second portion disposed over and electrically connected to the first portion. A semiconductor device having the semiconductor package, a circuit substrate and a circuit board is also provided.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-Cheng Hou, Chien-Hsun Lee, Chung-Shi Liu, Jung-Wei Cheng, Tsung-Ding Wang
  • Packages with Stacked Dies and Methods of Forming the Same
    Publication number: 20210050332
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Chien-Hsun Lee, Tsung-Ding Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Method for manufacturing semiconductor package with connection structures including via groups
    Patent number: 10916519
    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Electronics card including multi-chip module
    Patent number: 10916529
    Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jiun Yi Wu
  • Multi-Die Package Structures Including Redistribution Layers
    Publication number: 20210028147
    Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Tsung-Ding Wang, Chien-Hsun Lee
  • INTERCONNECT STRUCTURE
    Publication number: 20210007215
    Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi WU, Chien-Hsun LEE, Chewn-Pu JOU, Fu-Lung HSUEH
  • Manufacturing method of circuit board and of semiconductor device including the same
    Patent number: 10888000
    Abstract: A manufacturing method of a circuit board includes the following steps. A conductive plate is provided. The conductive plate is patterned to form ducts. The patterned conductive plate is laminated with a core dielectric layer. The lamination leaves exposed a bottom surface of the patterned conductive plate. Through holes are opened in portions of the core dielectric layer within the ducts. A conductive material is formed in the through holes and over the core dielectric layer to produce a metallization layer electrically insulated from the patterned conductive plate. Dielectric layers and conductive layers are alternately stacked on an upper surface of the core dielectric layer. The conductive layers are electrically connected to the metallization layer.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Semiconductor device, circuit board structure and method of fabricating the same
    Patent number: 10869385
    Abstract: A circuit board structure includes a first core layer, a first build-up layer and a second build-up layer. The first core layer has a first surface and a second surface opposite to the first surface, wherein the first core layer includes a core dielectric material layer and at least one patterned conductive plate embedded within the core dielectric material layer, the core dielectric material layer includes a first sub-dielectric material and a second sub-dielectric material, and at least one interface exists in between the first sub-dielectric material and the second sub-dielectric material. The first build-up layer is disposed on the first surface of the first core layer, and the second build-up layer is disposed on the second surface of the first core layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Substrate design for semiconductor packages and method of forming same
    Patent number: 10867949
    Abstract: A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee, Chen-Hua Yu
  • Semiconductor device and method of manufacture
    Patent number: 10854552
    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
  • Packages with stacked dies and methods of forming the same
    Patent number: 10825798
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Tsung-Ding Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Methods of forming multi-die package structures including redistribution layers
    Patent number: 10804242
    Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Tsung-Ding Wang, Chien-Hsun Lee
  • Semiconductor package and manufacturing method thereof
    Patent number: 10790210
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yang Yu, Chien-Hsun Lee, Yu-Min Liang
  • Interconnect structure and method of manufacturing the same
    Patent number: 10785865
    Abstract: A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou, Fu-Lung Hsueh
  • Integrated Circuit Package and Method
    Publication number: 20200286803
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Circuit board, semiconductor device including the same, and manufacturing method thereof
    Patent number: 10772205
    Abstract: A structure, a semiconductor device and a manufacturing method thereof are provided. The structure includes a core layer and a build-up stack disposed on the core layer. The core layer includes a first core dielectric layer, a second core dielectric layer, through vias, and a patterned conductive plate. The second core dielectric layer is disposed on the first core dielectric layer. The through vias cross the first core dielectric layer and the second core dielectric layer. The patterned conductive plate is disposed on the first core dielectric layer and is electrically insulated from the through vias. The build-up stack includes interconnected conductive patterns electrically connected to the through vias. A bottom surface of the patterned conductive plate is coplanar with an interface of the first core dielectric layer and the second core dielectric layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • CIRCUIT BOARD, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
    Publication number: 20200275557
    Abstract: A manufacturing method of a circuit board includes the following steps. A conductive plate is provided. The conductive plate is patterned to form ducts. The patterned conductive plate is laminated with a core dielectric layer. The lamination leaves exposed a bottom surface of the patterned conductive plate. Through holes are opened in portions of the core dielectric layer within the ducts. A conductive material is formed in the through holes and over the core dielectric layer to produce a metallization layer electrically insulated from the patterned conductive plate. Dielectric layers and conductive layers are alternately stacked on an upper surface of the core dielectric layer. The conductive layers are electrically connected to the metallization layer.
    Type: Application
    Filed: January 9, 2020
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • CIRCUIT BOARD, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
    Publication number: 20200275552
    Abstract: A structure, a semiconductor device and a manufacturing method thereof are provided. The structure includes a core layer and a build-up stack disposed on the core layer. The core layer includes a first core dielectric layer, a second core dielectric layer, through vias, and a patterned conductive plate. The second core dielectric layer is disposed on the first core dielectric layer. The through vias cross the first core dielectric layer and the second core dielectric layer. The patterned conductive plate is disposed on the first core dielectric layer and is electrically insulated from the through vias. The build-up stack includes interconnected conductive patterns electrically connected to the through vias. A bottom surface of the patterned conductive plate is coplanar with an interface of the first core dielectric layer and the second core dielectric layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • CIRCUIT CARRIER AND MANIFACTURING METHOD THEREOF
    Publication number: 20200260595
    Abstract: A circuit carrier and a manufacturing method thereof are provided. The circuit carrier for coupling an electronic device includes a flexible structure and a circuit structure. The flexible structure includes a conductive pattern disposed on a surface of a first dielectric layer. The circuit structure includes a second dielectric layer overlying the surface of the first dielectric layer and a circuit layer disposed on the second dielectric layer and connected to the conductive pattern, The flexible structure is embedded in and electrically connected to the circuit structure, and a portion of the flexible structure extends out from an edge of the circuit structure to be plugged into the electronic device.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Substrate design for semiconductor packages and method of forming same
    Patent number: 10714359
    Abstract: A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee, Chen-Hua Yu