Abstract: The invention provides an ESD (Electrostatic Discharge) protection circuit including a clamp circuit, a switch element, and a detection circuit. The clamp circuit is coupled between an ESD bus and a ground node. The switch element is coupled between a supply node and the ESD bus. The detection circuit is configured to detect whether an ESD event occurs. When no ESD event occurs, the detection circuit closes the switch element, such that the ESD bus is coupled to the supply node. When the ESD event occurs, the detection circuit opens the switch element, such that the ESD bus is decoupled from the supply node.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: The invention provides an ESD (Electrostatic Discharge) protection circuit including a clamp circuit, a switch element, and a detection circuit. The clamp circuit is coupled between an ESD bus and a ground node. The switch element is coupled between a supply node and the ESD bus. The detection circuit is configured to detect whether an ESD event occurs. When no ESD event occurs, the detection circuit closes the switch element, such that the ESD bus is coupled to the supply node. When the ESD event occurs, the detection circuit opens the switch element, such that the ESD bus is decoupled from the supply node.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: An electrostatic discharge protection circuit is provided. First NMOS transistor is coupled to a power line. Second NMOS transistor is coupled between the first NMOS transistor and a ground. Detection unit provides a detection signal when an ESD event occurs at the power line. Trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal. Discharge path is formed from the power line to the ground via the first and second NMOS transistors. First PMOS transistor is coupled between the power line and a gate of the second NMOS transistor. Third NMOS transistor is coupled between the ground and the gate of the second NMOS transistor. Second PMOS transistor is coupled between the gates of the first and second NMOS transistors. Third PMOS transistor is coupled between the power line and the first PMOS transistor.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first NMOS transistor coupled to a power line, a second NMOS transistor coupled between the first transistor and a ground, a detection unit, providing a detection signal when an ESD event occurs at the power line, and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. The trigger unit includes a first PMOS transistor coupled between the power line and a gate of the second NMOS transistor, a fourth resistor, and a second PMOS transistor, having a gate coupled to the cathode of the diode for receiving the detection signal.

Abstract: An electrostatic discharge protection circuit is provided. First NMOS transistor is coupled to a power line. Second NMOS transistor is coupled between the first NMOS transistor and a ground. Detection unit provides a detection signal when an ESD event occurs at the power line. Trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal. Discharge path is formed from the power line to the ground via the first and second NMOS transistors. First PMOS transistor is coupled between the power line and a gate of the second NMOS transistor. Third NMOS transistor is coupled between the ground and the gate of the second NMOS transistor. Second PMOS transistor is coupled between the gates of the first and second NMOS transistors. Third PMOS transistor is coupled between the power line and the first PMOS transistor.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first NMOS transistor coupled to a power line, a second NMOS transistor coupled between the first transistor and a ground, a detection unit, providing a detection signal when an ESD event occurs at the power line, and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. The trigger unit includes a first PMOS transistor coupled between the power line and a gate of the second NMOS transistor, a fourth resistor, and a second PMOS transistor, having a gate coupled to the cathode of the diode for receiving the detection signal.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors.

Abstract: A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.

Abstract: A buffer device includes a first driving circuit coupled between a signal terminal of the buffer device and a first reference potential, a current-limiting component including a first terminal coupled to the signal terminal, and a second driving circuit coupled between a second terminal of the current-limiting component and a second reference potential, wherein the current-limiting component limits an amount of ESD current flowing through the second driving circuit, and makes an amount of ESD current flowing through the first driving circuit be larger than the amount of ESD current flowing through the second driving circuit.

Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Abstract: A buffer device includes a first driving circuit coupled between a signal terminal of the buffer device and a first reference potential, a current-limiting component including a first terminal coupled to the signal terminal, and a second driving circuit coupled between a second terminal of the current-limiting component and a second reference potential, wherein the current-limiting component limits an amount of ESD current flowing through the second driving circuit, and makes an amount of ESD current flowing through the first driving circuit be larger than the amount of ESD current flowing through the second driving circuit.

Abstract: A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.

Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Abstract: A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

Abstract: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.