ESD Protection Devices
An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.
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This application is a Divisional of pending U.S. patent application Ser. No. 12/125,241, filed May 22, 2008 and entitled “ESD PROTECTION DEVICES”, which claims the benefit of U.S. Provisional Application No. 60/940,467, filed on May 29, 2007, and U.S. Provisional Application No. 60/956,132, filed on Aug. 16, 2007, the entirety of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to an ESD protection device, and more particularly to an SCR-based ESD protection device.
2. Description of the Related Art
Electrostatic discharge (ESD) damage has become one of the main reliability concerns facing integrated circuit (IC) products. Particularly, when scaled down to the deep sub-micron regine, integrated circuits become more vulnerable to ESD stress. Semiconductor controlled rectifier (SCR) devices had been used as an ESD protection device to protect complementary metal oxide semiconductor (CMOS) integrated circuit against damage. The SCR devices have the advantage of low holding voltage, which results in less power dissipation in the SCR devices under the ESD event than other ESD protection devices, such as thin oxide NMOS, or diode, in the CMOS technologies. Thus, the SCR devices can sustain much higher ESD voltage with a smaller layout area.
MOS transistors and SCR devices are both efficient protection devices, however, the MOS transistors are widely used in the industry. This is because the SCR device used for an ESD protection in deep submicron CMOS technologies has the latch-up issue.
Thus, it is desired to provide a novel SCR device structure with lath-up free to protect integrated circuits in low operating voltage application.
BRIEF SUMMARY OF THE INVENTIONOne exemplary embodiment of an ESD protection device comprises a substrate, a first doping region, a first MOS transistor structure, a second MOS transistor structure, a sixth doping region, and a first well region. The first doping region is formed in the substrate and encloses an active region, wherein the first doping region is coupled to a first node. The first MOS transistor structure is on the internal of the active region and comprises a second doping region, a third doping region, and a first gate. The second doping region is formed in the substrate and comprises a first portion and a second portion, wherein the second doping region is coupled to the first node. The third doping region is formed in the substrate. The first gate is formed on the substrate and between the second portion of the second doping region and the third doping region.
The second MOS transistor structure is on the internal of the active region and comprises a fourth doping region, a fifth doping region, and a second gate. The fourth doping region is formed in the substrate and comprises a first portion and a second portion, wherein the fourth doping region is coupled to a second node. The fifth doping region is formed in the substrate. The second gate is formed on the substrate and between the first portion of the fourth doping region and the fifth doping region. The third doping region is near the second portion of the fourth doping region, and the fifth doping region is near the first portion of the second doping region. The sixth doping region is formed in the substrate and on one side of the first and second MOS transistor structures, wherein the sixth doping region is coupled to the second node. The first well region is on the internal of the active region and formed in the substrate and under one part of the third doping region, one part of the fifth doping region, the fourth doping region, and the sixth doping region.
Another exemplary embodiment of an ESD protection device comprises a substrate, first to sixth doping regions, first and second gates, and a first well region. The first doping region is formed in the substrate and coupled to a first node. The second doping region is formed in the substrate and encloses the first doping region, wherein the second doping region comprises a first portion and a second portion and is coupled to the first node. The third doping region is formed in the substrate and encloses the first portion of the second doping region, wherein the third doping region has a first opening. The first gate is formed on the substrate and between the first portion of the second doping region and the third doping region. The fourth doping region is formed in the substrate and encloses the second portion of the second doping region, wherein the fourth doping region has an second opening corresponding to the first opening. The fifth doping region is formed in the substrate and comprises a first portion and a second portion, wherein the first portion of the fifth doping region encloses the third doping region, and the second portion thereof encloses the fourth doping region. The second gate is formed in the substrate and between the second of the fifth doping region and the fourth doping region. The sixth doping region is formed in the substrate and encloses the fifth doping region, wherein the fifth and sixth doping regions are coupled to a second node. The first well region is formed in the substrate and under the first doping region, the second doping region, one part of the third doping region, and one part of the fourth doping region.
Another exemplary embodiment of an ESD protection device comprises a first SCR and an ESD detection circuit. The first SCR is coupled between a high voltage source and a ground. The ESD detection circuit detects whether an ESD event occurs. When the ESD detection circuit detections that the ESD event occurs, the ESD detection circuit provides a first voltage and a second voltage to the first SCR, so that the first SCR provides a first discharging path.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
In this embodiment, the SCR 1 comprises two MOS transistor structures. One MOS transistor structure comprises the N+ doping regions 16 and 17 and the gate G10, the other comprises the P+ doping regions 14 and 15 and the gate G11. The N+ doping region 16 is formed in the substrate 10 and comprises a first portion and a second portion. The N+ doping region 17 is formed in the substrate and near the second portion potion of the N+ doping region 16. The gate G10 is formed on the substrate 10 and between the second portion of the N+ doping region 16 and the N+ doping region 17. The P+ doping region 14 is formed in the substrate 10 and near the first portion of the N+ doping region 16. The P+ doping region 15 is formed in the substrate 10 and comprises a first portion and a second portion. The second portion of the P+ doping region 15 is near the N+ doping region 17. The gate G11 is formed on the substrate 10 and between the first portion of the P+ doping region 15 and the P+ doping region 14. The well region 12 is formed in the substrate 10 and under one part of the P+ doping region 14, one part of the N+ doping region 17, the P+ doping region 15, and the N+ doping region 18. The N+ doping region 18 is formed in the substrate 10 and on one side of these two MOS transistor structures. Referring to
Referring to
Referring to the equivalent circuit in
Referring to
The N+ doping region 68 is formed in the substrate and comprises a first portion and a second portion. The first portion of the N+ doping region 68 encloses the P+ doping region 64, and the second portion thereof encloses the N+ doping region 67. The gate G61 is formed in the substrate and between the second portion of the N+ doping region 68 and the N+ doping region 67. The P+ doping region 65 is formed in the substrate and encloses the N+ doping region 68. The isolation structure 70 is formed in the substrate and between the N+ doping region 68 and the P+ doping region 65. The N-type well region 62 is formed in the substrate and encloses the P+ doping region 65. The isolation structure 71 is formed in the substrate and between the N-type well region 62 and the P+ doping region 65. The N+ doping region 69 is formed in the N-type well region 62. The N-type well region 61 is formed in the substrate and under the N+ doping region 66, the P+ doping region 63, one part of the P+ doping region 64, and one part of the N+ doping region 67. Moreover, the P+ doping region 63 and the N+ doping region 66 are coupled to one node, and the P+ doping region 65 and the N+ doping region 68 are coupled to the other node.
According to the structure of the SCR 6, there are four MOS transistor structures to form four MOS transistors. The P+ doping regions 63 and 64 and the gate G60 constitute two MOS transistors, and the N+ doping regions 67 and 68 and the gate G61 constitute the other two MOS transistors. When the SCR 6 is applied with an ESD detection circuit, such as the ESD detection circuit 30 of
Each of the above SCRs 1, 4, 5 and 6 can be coupled between an I/O pad and a ground GND. Referring to
The ESD detection circuit 75 is coupled between the high voltage source VDD and the ground GND and detects whether an ESD event occurs. In normal mode, the ESD detection circuit 75 provides a low voltage and a high voltage respectively to the gates G10 and G11 of the SCRs 72a-72b to turn off the MOS transistors 31 and 32 thereof. When detecting that the ESD event occurs, the ESD detection circuit 75 provides a high voltage and a low voltage respectively to the gates G10 and G11 of the SCRs 72a-72b to turn on the MOS transistors 31 and 32 thereof, so that each of the SCRs 72a-72b provides a discharging path.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. An ESD protection device comprising:
- a first semiconductor controlled rectifier (SCR) coupled between a high voltage source and a ground; and
- an ESD detection circuit detecting whether an ESD event occurs;
- wherein when the ESD detection circuit detects that the ESD event occurs, the ESD detection circuit provides a first voltage and a second voltage to the first SCR, so that the first SCR provides a first discharging path.
2. The ESD protection device as claimed in claim 1 further comprising a second SCR coupled between an I/O pad and the ground, wherein when the ESD detection circuit detects that the ESD event occurs, the ESD detection circuit provides the first voltage and the second voltage to the second SCR, so that the second SCR provides a second discharging path.
3. The ESD protection device as claimed in claim 2, wherein each of the first and second SCRs comprises:
- a first MOS transistor having a gate, a source coupled to a first node, and a drain coupled to a second node;
- a first BJT transistor having a base coupled to a third node, an emitter coupled to the first node, and a collector coupled to the second node;
- a first resistance coupled between the first and third nodes;
- a second MOS transistor having a gate, a drain coupled to the third node, and a source coupled to a fourth node;
- a second BJT transistor having a base coupled to the second node, a collector coupled to the third node, and an emitter coupled to the fourth node; and
- a second resistor coupled between second and fourth nodes.
4. The ESD protection device as claimed in claim 3, wherein the gates of the first MOS transistors of the first and second SCRs receive the first voltage, and the gates of the second MOS transistors of the first and second SCRs receive the second voltage.
5. The ESD protection device as claimed in claim 4, wherein the first node of the first SCR is coupled to the high voltage source, and the fourth node of the first SCR is coupled to the ground.
6. The ESD protection device as claimed in claim 5, wherein the first node of the second SCR is coupled to the I/O pad, and the fourth node of the second SCR is coupled to the ground.
Type: Application
Filed: Apr 25, 2011
Publication Date: Sep 8, 2011
Applicant: MEDIATEK INC. (Hsin-Chu)
Inventor: Chien-Hui Chuang (Sindian City)
Application Number: 13/093,589
International Classification: H01L 27/08 (20060101);