Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Abstract: A ring oscillator having a stable output signal without influence of MOS devices is disclosed. The ring oscillator has a bias circuit to drive a plurality of delay cells. The bias circuit has a first loading unit with a p-n junction, a second loading unit with a p-n junction, and a resistor electrically connected to the p-n junction of the second loading unit. The second loading unit and the resistor are positioned at a current path of a current mirror, and the first loading unit is positioned at another current path of the current mirror. The area of the p-n junction in the second loading unit is not equal to the area of the p-n junction in the first loading unit. The magnitudes of the current passing on the two current paths are only controlled by characteristics of the p-n junctions of the first and second loading units.

Abstract: A ring oscillator having a stable output signal without influence of MOS devices is disclosed. The ring-oscillator has a bias circuit to drive a plurality of delay cells. The bias circuit has a first loading unit with a p-n junction, a second loading unit with a p-n junction, and a resistor electrically connected to the p-n junction of the second loading unit. The second loading unit and the resistor are positioned at a current path of a current mirror, and the first loading unit is positioned at another current path of the current mirror. The area of the p-n junction in the second loading unit is not equal to the area of the p-n junction in the first loading unit. The magnitudes of the current passing on the two current paths are only controlled by characteristics of the p-n junctions of the first and second loading units.

Abstract: A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.

Abstract: The present invention includes a nonvolatile memory structure comprising: nonvolatile memory cell area including write/erase pins, address pins and data input/output pins; conductive contact pads arranged at the periphery area of the nonvolatile memory cell area for power input to operate the nonvolatile memory cell, wherein the conductive contact pads are connected to a power selecting from a positive power, a negative power or the combination thereof. The conductive contact pads include a positive power pin or a negative power pin for providing the operating power.

Abstract: A voltage recovery switch for neutralizing a first voltage and a second voltage in a non-volatile memory. The voltage recovery switch includes a first PMOS transistor having a gate electrically connected to a third voltage and a source electrically connected to the first voltage, an NMOS transistor having a gate electrically connected to a control signal and a drain electrically connected to a drain of the first PMOS transistor, and a second PMOS transistor having a gate electrically connected to a fourth voltage, a source electrically connected to the source of the NMOS transistor, and a drain electrically connected to the second voltage.

Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Abstract: A word line driver includes an address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the address decoder. A method of driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.

Abstract: A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.

Abstract: A two-stage negative level shifting circuit for preventing field breakdown due to an excessive voltage shift. The first stage has a first voltage distributor and a first driver and the second stage has a second voltage distributor and a second driver. In the first stage, an input voltage shifting between a positive voltage and a ground voltage is converted into a voltage shifting between a first negative voltage and the ground voltage. In the second stage, the voltage is further converted into a voltage shifting between the ground voltage and a second negative voltage, which has a larger absolute magnitude than the first negative voltage.

Abstract: A two-stage negative level shifting circuit for preventing field breakdown due to an excessive voltage shift. The first stage has a first voltage distributor and a first driver and the second stage has a second voltage distributor and a second driver. In the first stage, an input voltage shifting between a positive voltage and a ground voltage is converted into a voltage shifting between a first negative voltage and the ground voltage. In the second stage, the voltage is further converted into a voltage shifting between the ground voltage and a second negative voltage, which has a larger absolute magnitude than the first negative voltage.