Abstract: A lens assembly and Augmented Reality (AR) glasses, including a waveguide substrate, a wiring layer, a protective layer, an eye tracking component, and a lens. The waveguide substrate includes a first surface. The wiring layer is disposed on the first surface. The protective layer is disposed on the first surface and covering the wiring layer. The eye tracking component is disposed in the protective layer and is electrically connected with the wiring layer for tracking position of an eyeball. The lens is connected to a side of the protective layer away from the waveguide substrate. The AR glasses includes a display device and two lens assemblies. The display device is positioned between the two lens assemblies for emitting image light to the waveguide substrates of the two lens assemblies.

Abstract: A package structure includes a carrier substrate and a die. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The semiconductor substrate is located between the conductive posts and the carrier substrate.

Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.

Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, an obstacle sensor, a memory storing instructions, and a processor coupled to the one or more motors, the obstacle sensor, and the memory. The processor is configured to execute the instructions to cause the UGV to obtain location information of multiple navigation points; calculate a navigation path based on the obtained location information; drive the one or more motors to navigate the UGV along the navigation path; detect, by the obstacle sensor, whether one or more obstacles exist while navigating the UGV, and if detected, determine location information of the one or more obstacles; and if the one or more obstacles are detected by the obstacle sensor, update the navigation path based on determined location information of the one or more obstacles.

Abstract: An embodiment phase change material switch may include a first phase change material element, a second phase change material element, a first conductor electrically connected to a first end of each of the first phase change material element and the second phase change material element such that the first conductor is configured as a first terminal of an electrical circuit having a parallel configuration, a second conductor electrically connected to a second end of each of the first phase change material element and the second phase change material element such that the second conductor is configured as a second terminal of the electrical circuit having the parallel configuration, and a heating device coupled to the first phase change material element and to the second phase change material element and configured to supply a heat pulse to the first phase change material element and to the second phase change material element.

Abstract: A semiconductor device includes a semiconductor substrate having a first source/drain region, a semiconductor layer, a first floating gate electrode, a first control gate electrode, a second floating gate electrode, a second control gate electrode, and an erase gate electrode. The semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode laterally surrounds the first semiconductor layer. The first control gate electrode laterally surrounds the first floating gate electrode and the first semiconductor layer. The second floating gate electrode laterally surrounds the first semiconductor layer. The second control gate electrode laterally surrounds the second floating gate electrode and the semiconductor layer.

Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

Abstract: A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.

Abstract: A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A method of manufacturing an integrated circuit includes following operations. A stack of a plurality pair of first layers and second layers alternately arranged is formed over a substrate. A plurality of first holes is formed in the stack. An isolation layer is formed to cover sidewalls of the first holes. A plurality of conductive features is formed in the first holes. A plurality of second holes are formed in the stack. Each of the second holes exposes a portion of a sidewall of at least one of the conductive features. A channel layer is formed to cover sidewalls of the second holes and the portions of the sidewalls of the conductive features. The second layers of the stack are replaced with a plurality of gate layers.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A tool detector including a right-angle triangular base and an automatic controller is revealed. A light source of the right-angle triangular base emits a main light ray to a plane mirror to generate a reflected light ray which is incident to a quadrant detector to create a light receiving area. The automatic controller is for measuring a tool length and a tool radius. A control device of a computer numerical control machine tool sets up a standard value by a standard bar and drives an unfinished tool and a processed tool to set up an original value set and a measured value set. The automatic controller performs an error analysis on the original and measured value sets to get a relative difference of a tool length and radius of the processed tool for measuring the tool length and radius and compensation of thermal variables of the CNC machine tool.

Abstract: Some implementations described herein provide an inductor device formed in a substrate of a semiconductor device including an integrated circuit device. The inductor device may use one or more conduction layers that are included in the substrate. Furthermore, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, an electrical circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.