Patents by Inventor Chien-Hung Liu

Chien-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098475
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 10950703
    Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien Hung Liu
  • Publication number: 20210074715
    Abstract: A method of forming a memory device is provided. The method comprises: forming a first storage portion on a substrate; forming a conductive layer on the first storage portion, wherein the conductive layer has a first surface coupled to the first storage portion; and forming a second storage portion on a second surface of the conductive layer, wherein the second surface is opposite to the first surface.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventor: CHIEN HUNG LIU
  • Publication number: 20210066456
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Yun-Chi WU, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 10935326
    Abstract: A thermal conducting structure includes a vapor chamber and at least one heat pipe. The vapor chamber has a casing with a through hole formed on a side of the casing, and a chamber defined inside the casing and communicated with the through hole and having a metal mesh covered on an inner wall of the chamber. The heat pipe has a tubular body and an opening formed at an end of the tubular body, and the tubular body is connected to the through hole, and a cavity is defined inside the tubular body. A capillary member is covered onto an inner wall of the cavity. The metal mesh extends through the opening into the cavity to connect the capillary member. The metal mesh is used as a capillary structure, and the vapor chamber and heat pipe are used together to provide a better cooling efficiency.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 2, 2021
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Chien-Hung Sun, Te-Hsuan Chin, Lei-Lei Liu
  • Patent number: 10928743
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Chia-Hung Kao, Hsiu-Jen Wang, Shih-Hao Kuo, Yi-Sheng Liu, Shih-Hsien Lee, Ching-Chang Chen, Tsu-Hui Yang
  • Publication number: 20210043161
    Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Inventors: Chao-Tung YANG, Wei-Hung CHEN, Shih-Hsun LIN, Wei-Jyun TU, Chun-Hong LIU, Chien-Chung LIN, Chieh-Yuan LO, Hsiao-Ling CHANG
  • Publication number: 20210035937
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 10878915
    Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 10879256
    Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Hung Liu, Chih-Wei Hung
  • Patent number: 10877249
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, and a fifth lens. At least one lens among the first to the fifth lenses has positive refractive force. The fifth lens can have negative refractive force, wherein both surfaces thereof are aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the fifth lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Ability Opto-Electronics Technology Co., Ltd.
    Inventors: Yeong-Ming Chang, Chen-Hung Tsai, Chien-Hsun Lai, Yao-Wei Liu
  • Patent number: 10879258
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 10854618
    Abstract: A memory device includes: a conductive layer coupled to a reference voltage level; a first storage portion vertically coupled to a first surface of the conductive layer; and a second storage portion vertically coupled to a second surface of the conductive layer; wherein the second surface is opposite to the first surface.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien Hung Liu
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10840333
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
  • Publication number: 20200357651
    Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Hsin-Hung LIAO, Chung-Shi LIU
  • Patent number: 10823904
    Abstract: A display device includes at least one display module and a backlight module. The display module includes display units and N driving chips. The N driving chips are arranged along a first direction and electrically connected to the display units. The display units are connected and arranged in N rows in the first direction and M columns in a second direction. N and M are respectively greater than or equal to 1. The backlight module includes a light bar assembly adapted to be disposed below a column of the M columns of the display units farthest from the driving chips, and a length of the light bar assembly corresponds to that of the display units along the first direction. The light bar assembly includes at least one first light bar unit. A length of each first light bar unit is X times the length of each display unit along the first direction, and X is greater than or equal to 1.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 3, 2020
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Ting Fu, Kun-Hung Hsieh, Chun-Liang Lin, Ren-Wei Huang, Hsin-Chen Lu, Min-Chieh Chen, Chien-Pang Liu, Yen-Ling Chen
  • Patent number: 10823849
    Abstract: A tracking-distance-measuring system capable of tracking a torso object is provided. The tracking-distance-measuring system includes: an image sensor, a controller, a distance-measuring device, and an actuator device. The image sensor is configured to capture an input image. The controller is configured to analyze the input image to recognize a torso object from the input image, and calculate an offset distance between a center of the torso object and a central axis of the input image. The actuator device is configured to carry the distance-measuring device. The controller controls the actuator device to calibrate an offset angle between the distance-measuring device and the recognized torso object according to the offset distance. In response to calibrating the offset angle, the distance-measuring device emits energy and receives reflected energy to detect an object distance of the torso object.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 3, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Chien-Hung Liu
  • Patent number: 10816757
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, and a fifth lens. At least one lens among the first to the fifth lenses has positive refractive force. The fifth lens can have negative refractive force, wherein both surfaces thereof are aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the fifth lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 27, 2020
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yeong-Ming Chang, Chen-Hung Tsai, Chien-Hsun Lai, Yao-Wei Liu
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang