Abstract: A semiconductor device includes a substrate, an outer detection wire and an inner detection wire. The substrate has a periphery lateral surface. The outer detection wire is disposed on the substrate and adjacent to the periphery lateral surface. The inner detection wire is disposed on the substrate, adjacent to the periphery lateral surface, and isolated from the outer detection wire. The outer detection wire is closer to the periphery lateral surface than the inner detection wire.

Abstract: A semiconductor device includes a first semiconductor component, a second semiconductor component, and a damage detection structure. The first semiconductor component includes a first edge region. The second semiconductor component is stacked below the first semiconductor component and includes a second edge region. The damage detection structure includes a plurality of first conductive paths and a plurality of second conductive paths. The first conductive paths are disposed in the first edge region. The second conductive paths are disposed in the second edge region and are electrically coupled to the first conductive paths.

Abstract: The present disclosure provides a semiconductor package including a first integrated circuit die having a first on-die test ring thereon; a second integrated circuit die having a second on-die test ring thereon; and a system test ring constructed by connecting the first on-die test ring and the second on-die test ring. The system test ring allows for detection of damage to the individual integrated circuit die assembled in one package on a system level.

Abstract: A semiconductor die includes a substrate comprising an integrated circuit region thereon, a front end of line (FEOL) portion disposed on a front side of the substrate, a back end of line (BEOL) portion disposed on the FEOL portion, a power delivery network (PDN) portion disposed on a back side of the substrate, and a plurality of through substrate vias penetrating through the substrate and disposed along a perimeter of the integrated circuit region. The BEOL portion includes a first discontinuous ring disposed along the perimeter of the integrated circuit region. The PDN portion includes a second discontinuous ring disposed along the perimeter of the integrated circuit region. The first discontinuous ring is interlaced with the second discontinuous ring through the plurality of through substrate vias, thereby constituting a die damage ring.

Abstract: A semiconductor device includes an application processor (AP) die and a memory die directly bonded to the AP die. The memory die includes a substrate, a non-volatile memory structure on the substrate, and at least one trench capacitor in the substrate.

Abstract: A missing data compensation method, missing data compensation system and non-transitory computer-readable medium are provided in this disclosure. The method includes the following operations: inputting a sensing signal by a sensor; searching for a historical data sections similar to a first data section from the plurality of historical data sections to generate a plurality of candidate data sections; calculating a plurality of data relation diagrams according to the first data section and the candidate data sections, respectively; utilizing a feature recognition model to calculate a plurality of similarity values according to the data relation diagrams; selecting a candidate data section corresponding to the maximum similarity value as a sample data section; and utilizing the data in the sample data section to compensate the data in the first data section to generate compensated data section.

Abstract: A missing data compensation method, missing data compensation system and non-transitory computer-readable medium are provided in this disclosure. The method includes the following operations: inputting a sensing signal by a sensor; searching for a historical data sections similar to a first data section from the plurality of historical data sections to generate a plurality of candidate data sections; calculating a plurality of data relation diagrams according to the first data section and the candidate data sections, respectively; utilizing a feature recognition model to calculate a plurality of similarity values according to the data relation diagrams; selecting a candidate data section corresponding to the maximum similarity value as a sample data section; and utilizing the data in the sample data section to compensate the data in the first data section to generate compensated data section.

Abstract: A device recommendation system includes an environmental monitoring module, a device monitoring module, an abnormality monitoring module and a decision module. The environmental monitoring module receives environmental data obtained by environmental sensors and generates environmental history data accordingly. The device monitoring module retrieves enablement counts from electronic devices and generates enablement history data accordingly. The abnormality monitoring module determines whether the environmental data exceeds a threshold in a first time section and generates an abnormal signal accordingly. According to the abnormal signal, the decision module calculates the environmental history data based on an initial weight matrix to generate a recommendation data used to change the enablement status of the electronic devices.

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A springless shooting dart composed of a hollow cylinder, a shuttle, a rope, and a dart is provided. Inside the hollow cylinder is a shuttle. A dart can be disposed at the front end of the shuttle. The shuttle is connected to a rope having one end tied to the user's waist. A user can control the dart to be shot out by holding on to the cylinder and extending from his arm.

Abstract: A chair adjustable device includes a base with which a seat frame and a backrest frame are respectively and pivotably connected. A positioning mechanism is connected to the base and includes an operation handle which is able to shift a transmission frame and a positioning plate is movably connected to the transmission frame and biased by a spring, so that the positioning plate can be movably engaged with one of notches defined in a positioning member on the seat frame. The seat frame and the backrest frame are connected by a connection member so that the chair can be adjusted its tilt angle by operating the operation handle.

Abstract: A pressing board operation mechanism for paper cutter includes an eccentric driving rod to pivot a first link assembly composed of two pairs of triangular plates and the first link assembly is connected to a second link assembly which includes a rack member, two first links and two second links. The two first links are operationally connected to the rack member by two respective rack ends and the two second links are pivotably connected between the first links and the pressing board which is lowered or lifted by the pivotal movement of the first and second links. Two sensors are provided and activated when the first link assembly is moved to a pre-set positions and the sensors send commands to stop the motor.

Abstract: A chair adjustable device includes a base with which a seat frame and a backrest frame are respectively and pivotably connected. A positioning mechanism is connected to the base and includes an operation handle which is able to shift a transmission frame and a positioning plate is movably connected to the transmission frame and biased by a spring, so that the positioning plate can be movably engaged with one of notches defined in a positioning member on the seat frame. The seat frame and the backrest frame are connected by a connection member so that the chair can be adjusted its tilt angle by operating the operation handle.