Patents by Inventor Chien-Kuo Chang

Chien-Kuo Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272919
    Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Patent number: 11088109
    Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Pu-Sheng Lee, Fu-Jen Li, Hsien-Liang Meng
  • Patent number: 11011487
    Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
  • Patent number: 11011431
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Publication number: 20200411385
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Publication number: 20200321297
    Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Patent number: 10777467
    Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Patent number: 10700030
    Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
  • Publication number: 20200161275
    Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 21, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Pu-Sheng LEE, Fu-Jen LI, Hsien-Liang MENG
  • Publication number: 20200066598
    Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Publication number: 20200058611
    Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Application
    Filed: January 28, 2019
    Publication date: February 20, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Patent number: 10468307
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Publication number: 20190318987
    Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Inventors: CHIH-HAO LIN, CHIEN-KUO CHANG, TZU-KAI LAN, HUI-TING LIN, CHUN-MIN LIN
  • Publication number: 20190088552
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Patent number: 10039378
    Abstract: An adjustable table includes a table board, an inclining structure, a supporting structure, and a foot structure. The table board is provided with a pivoting portion on one end thereof. The inclining structure is provided with a mounting portion on one end thereof, and the mounting portion is pivotally combined with the pivoting portion of the table board, such that the table board and the inclining structure pivotally sway to open and close. The supporting structure is combined between the table board and the inclining structure for supporting and fixing the table board and the inclining structure. The foot structure is pivotally combined with the inclining structure, such that the inclining structure sways toward the foot structure.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 7, 2018
    Assignee: PRODUCT DEPOT INTERNATIONAL CORP.
    Inventor: Chien-Kuo Chang
  • Publication number: 20180206630
    Abstract: A table with adjustable height and inclination includes a foot; a first support rack clutchably and pivotally combined with the foot; a second support rack clutchably and pivotally combined with the first support rack and fixed to a table board; a first positioning assembly rotatably disposed at a location of the pivotal combination between the first support rack and the foot for adjusting and fixing an angle of the first support rack swaying against the foot; and a second positioning assembly rotatably disposed at a location of the pivotal combination between the first support rack and the second support rack for adjusting and fixing an angle of the second support rack swaying against the first support rack.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventor: CHIEN-KUO CHANG
  • Publication number: 20180140090
    Abstract: An adjustable table includes a table board, an inclining structure, a supporting structure, and a foot structure. The table board is provided with a pivoting portion on one end thereof. The inclining structure is provided with a mounting portion on one end thereof, and the mounting portion is pivotally combined with the pivoting portion of the table board, such that the table board and the inclining structure pivotally sway to open and close. The supporting structure is combined between the table board and the inclining structure for supporting and fixing the table board and the inclining structure. The foot structure is pivotally combined with the inclining structure, such that the inclining structure sways toward the foot structure.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Inventor: CHIEN-KUO CHANG
  • Patent number: 9805997
    Abstract: Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling a ring to a substrate, and coupling an integrated circuit die to the substrate within the ring. A molding material is disposed around the integrated circuit die within the ring.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Chien-Kuo Chang, Wei-Ting Lin, Kuan-Lin Ho, Chin-Liang Chen, Shih-Yen Lin
  • Patent number: 9666556
    Abstract: An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Chien-Kuo Chang, Chi-Yang Yu, Jing Ruei Lu, Chih-Hao Lin
  • Patent number: D873586
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 28, 2020
    Inventor: Chien-Kuo Chang