Abstract: Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

Abstract: A slide rail kit is applicable to a rack. The slide rail kit includes a first rail and a locking member. The first rail is arranged with a mounting feature. The locking member is arranged on the first rail. The mounting feature is configured to mount the first rail to a mounting structure of the rack. The locking member includes a locking part and an operating part. The locking part is configured to be held in a state being blocked by the rack in response to an elastic force of an elastic structure. The operating part is configured to be operated to move the locking part away from the state being blocked by the rack.

Abstract: An IC structure and methods of forming the same are described. In some embodiments, the structure includes a fin structure disposed over a substrate, the fin structure includes first and second segments and a bottom surface between the first and second segments, and the bottom surface includes a plurality of recesses. The structure further includes a dielectric material disposed between the first and second segments of the fin structure, and the dielectric material is disposed on the bottom surface and in the plurality of recesses. The structure further includes a gate structure disposed over the first segment of the fin structure, and the gate structure covers a top surface and side surfaces of the first segment of the fin structure.

Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: A portable exercise apparatus includes a first main body, a second main body, a seat, a pedal and at least two resistance units. The second main body is connected to the first main body, the first main body and the second main body are foldable relative to each other so as to be in a folded mode or an expanded mode. The seat can be slidably disposed on the first main body when the first main body and the second main body are in the expanded mode and the pedal is in a slanted position. Each of the two resistance units has a resistance source that can provide a resistance force. When the first main body and the second main body are in the folded mode, the resistance sources of the two resistance units are respectively arranged in the two receiving spaces.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: An internal radio wave transmission system of building includes a base layer and a transmission layer, with a radio wave transmission channel between the two layers. The radio wave transmission system in a building includes a signal transceiver device, a first reflective plate and a second reflective plate. The signal transceiver device is connected with a telecommunication room, and the signal transceiver device emits and receives radio wave signals. The first reflective plate is disposed in the channel and corresponds to positions of the base layer and the signal transceiver device to receive and guide the radio wave signals. The second reflective plate is disposed in the channel and corresponds to a position of the transmission layer to receive and guide the radio wave signals to terminal equipment located in the transmission layer. The invention ensures the effective transmission of the radio wave signals inside the building.

Abstract: Provided are a silicon carbide crystal growth device and a quality control method. The device includes: an annealing unit, a crystal growth unit, an atmosphere control unit, and a transport system; the atmosphere control unit provides a gas environment with low water, oxygen and nitrogen; the transport system transports a plurality of target objects after high-temperature purification by the annealing unit to the atmosphere control unit; after assembling silicon carbide seed crystal and silicon carbide powder in a graphite crucible and covering with thermal insulation material to form a container inside the atmosphere control unit, the transport system transports the container to the crystal growth unit. The method uses a weighing system in a chamber of the crystal growth unit to detect a weight change of silicon carbide seed crystal and silicon carbide powder during a crystal growth process through a plurality of weight sensors of the weighing system.

Abstract: An embodiment semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region over a surface of the package substrate and the capillary underfill material may be formed over a second region of the surface of the package substrate, such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame partially surrounding the first semiconductor die and the second semiconductor die such that a multi-die chip is formed that includes the first semiconductor die, the second semiconductor die, and the multi-die frame.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.

Abstract: Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Abstract: A method is provided, including bonding a semiconductor device to a surface of a package substrate; placing a lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the lid and the top surface of the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the lid downward so that the molten metal TIM laterally flows beyond the boundary of the semiconductor device, and the shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a convex arc; lifting the lid upward so that the molten metal TIM laterally flows back, and the shape of the lateral sidewall of the molten metal TIM in the longitudinal section is a concave arc; and bonding the lid to the semiconductor device through the metal TIM by cooling the molten metal TIM.

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.