Abstract: A communication device includes a Bluetooth earphone device, a Bluetooth controller device and a walkie-talkie device. The Bluetooth earphone device includes an earphone body, and a first Bluetooth transceiver configured to transmit and receive voice signals. The Bluetooth controller device includes a controller operation button, and a first Bluetooth Low Energy transceiver configured to transmit a controller talk signal when the controller operation button is triggered. The walkie-talkie device includes a walkie-talkie body configured to transmit and receive wireless communication signals, a second Bluetooth transceiver and a second Bluetooth Low Energy transceiver.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: A power supply system with current sharing includes a current sharing bus, a plurality of power supply units, and a plurality of controllers. The power supply units are connected to each other through the current sharing bus. Each power supply unit provides a current sharing signal value to the current sharing bus, and provides an output current to a load. Each controller receives current sharing signal values provided from other power supply units and current signal values corresponding to the output currents. When determining that the current signal value is less than a reference current sharing signal value, the controller increases an output voltage of the power supply unit to increase the output current. Otherwise, the controller decreases the output voltage to decrease the output current so that so that the output currents of the power supply units are shared to supply power to the load.

Abstract: A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for measuring the temperature of a wafer within an ion implantation system. An exemplary ion implantation system may include a robotic arm, one or more load lock chambers, a pre-implantation station, an ion implanter, a post-implantation station, and a controller. The pre-implantation station is configured to heat or cool a wafer prior to the wafer being implanted with ions by the ion implanter. The post-implantation station is configured to heat or cool a wafer after the wafer is implanted with ions by the ion implanter. The pre-implantation station and/or post-implantation station are further configured to measure a current temperature of a wafer. The controller is configured to control the various components and processes described above, and to determine a current temperature of a wafer based on information received from the pre-implantation station and/or post-implantation station.

Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.

Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

Abstract: A measuring equipment and a measuring method for measuring electronic properties and optical properties are disclosed. The measuring equipment is used to measure electronic and optical properties. The measuring equipment includes a test socket, a light-emitting element circuit, an optical device, a signal conversion circuit, and a control host. The test socket has measuring probes. The test socket tests the electronic properties of the semiconductor device through the measuring probes. The light-emitting element circuit has a light-emitting element. The optical device measures the optical properties of the light-emitting element. The signal conversion circuit converts the electronic properties to an electronic signal. The control host analyzes and stores the electronic signal and the optical properties.

Abstract: A method of updating power firmware is applied to update power firmware when a power supply is powered. The method is executed by a microcontroller of the power supply, and the method includes steps of: planning a memory space in the microcontroller as a first space and a second space, wherein the first space stores a first program currently executing the power supply required by the power supply, emptying the second space before the power firmware is updated, writing a second program stored in a management system into the second space, switching the second space to the first space to complete updating the power firmware after the second program is completely written into the second space, and continuously outputting working power.

Abstract: A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

Abstract: A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Abstract: Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.

Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.