Patents by Inventor Chien-Lin Chang Chien
Chien-Lin Chang Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240250030Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.Type: ApplicationFiled: January 23, 2023Publication date: July 25, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Chiu-Wen LEE, Yu-Hsun CHANG, Tai-Yuan HUANG
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Publication number: 20240155758Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
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Patent number: 11127650Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.Type: GrantFiled: February 24, 2020Date of Patent: September 21, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chiu-Wen Lee, Hung-Jung Tu, Chang Chi Lee, Chin-Li Kao
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Publication number: 20210265231Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chiu-Wen LEE, Hung-Jung TU, Chang Chi LEE, Chin-Li KAO
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Publication number: 20210265273Abstract: A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes at least one conductive via connecting to a pad of the plurality of semiconductor chips.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chiu-Wen LEE, Ian HU, Chang Chi LEE
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Patent number: 10541198Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.Type: GrantFiled: January 30, 2018Date of Patent: January 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
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Publication number: 20190378963Abstract: An electronic apparatus includes a substrate structure, a plurality of pillar bases, at least one light emitting device and a plurality of electrically connective materials. The substrate structure has a top surface and a bottom surface opposite to the top surface, and included a non III-V group material. The pillar bases are disposed adjacent to the top surface of the substrate structure. The light emitting device includes a III-V group material, and comprises a plurality of electrode pads. The electrically connective materials are interposed between the electrode pads of the light emitting device and the pillar bases.Type: ApplicationFiled: June 3, 2019Publication date: December 12, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ming-Te LIU, Chien Lin CHANG CHIEN, Chang Chi LEE
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Publication number: 20180337130Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.Type: ApplicationFiled: May 16, 2017Publication date: November 22, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chin-Li KAO, Shih-Yu WANG, Chang Chi LEE
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Patent number: 10134677Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.Type: GrantFiled: May 16, 2017Date of Patent: November 20, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chin-Li Kao, Shih-Yu Wang, Chang Chi Lee
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Patent number: 10037974Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.Type: GrantFiled: January 26, 2017Date of Patent: July 31, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chang Chi Lee, Chin-Li Kao, Dao-Long Chen, Ta-Chien Cheng
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Publication number: 20180158766Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.Type: ApplicationFiled: January 30, 2018Publication date: June 7, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chin-Li KAO, Chang Chi LEE, Chih-Pin HUNG
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Patent number: 9917043Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.Type: GrantFiled: April 4, 2017Date of Patent: March 13, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
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Publication number: 20170263589Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.Type: ApplicationFiled: January 26, 2017Publication date: September 14, 2017Inventors: Chien Lin CHANG CHIEN, Chang Chi LEE, Chin-Li KAO, Dao-Long CHEN, Ta-Chien CHENG
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Publication number: 20170207153Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chin-Li KAO, Chang Chi LEE, Chih-Pin HUNG
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Patent number: 9515234Abstract: A light emitting diode package includes a substrate, several light emitting diodes mounted on the substrate, and a package member enveloping the light emitting diodes. The light emitting diodes are electrically coupled to the substrate. The package member includes at least two layers, the first layer and the second layer. The first layer is spread on the substrate and completely covers the light emitting diodes and the wires. The second layer is formed on the first layer. Fluidity of colloid forming the second layer is worse than that of the first layer. A method is also provided to manufacture the present light emitting diode package.Type: GrantFiled: August 7, 2015Date of Patent: December 6, 2016Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: Chung-Min Chang, Chien-Lin Chang-Chien, Ya-Ting Wu
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Patent number: 9439280Abstract: An light emitting diode (LED) module includes a circuit board, a plurality of LED chips arranged on and electrically connected to the circuit board, and an encapsulant arranged on the circuit board and covering the LED chips, a plurality of first recesses defined in a first surface of the circuit board.Type: GrantFiled: September 2, 2014Date of Patent: September 6, 2016Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: Chung-Min Chang, Chien-Lin Chang-Chien, Ya-Ting Wu, Zheng-Hua Yang
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Publication number: 20160064629Abstract: A light emitting diode package includes a substrate, several light emitting diodes mounted on the substrate, and a package member enveloping the light emitting diodes. The light emitting diodes are electrically coupled to the substrate. The package member includes at least two layers, the first layer and the second layer. The first layer is spread on the substrate and completely covers the light emitting diodes and the wires. The second layer is formed on the first layer. Fluidity of colloid forming the second layer is worse than that of the first layer. A method is also provided to manufacture the present light emitting diode package.Type: ApplicationFiled: August 7, 2015Publication date: March 3, 2016Inventors: CHUNG-MIN CHANG, CHIEN-LIN CHANG-CHIEN, YA-TING WU
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Patent number: 9231174Abstract: An light emitting diode (LED) module includes a circuit board, a set of LED chips formed on and electrically connected to the circuit board, and an encapsulant arranged on the circuit board and covering the LED chips, a set of first recesses defined in a top surface of the encapsulant.Type: GrantFiled: September 2, 2014Date of Patent: January 5, 2016Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: Chung-Min Chang, Chien-Lin Chang-Chien, Ya-Ting Wu, Zheng-Hua Yang
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Patent number: 9166117Abstract: An exemplary light emitting device includes a blue-green light source and a orange-red light source. The blue-green light source emits blue-green light and the orange-red light source emits orange-red light when they are activated. The blue-green light and the orange-red light are mixed together to obtain white light.Type: GrantFiled: October 30, 2013Date of Patent: October 20, 2015Assignee: ADVANCED OPTOELECTRIC TECHNOLOGY, INC.Inventors: Chung-Min Chang, Chien-Lin Chang-Chien, Hsuen-Feng Hu, Chang-Wen Sun, Ya-Ting Wu
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Patent number: 9109782Abstract: An LED light emitting apparatus includes an LED light source, a light guiding device and an emitting window. The emitting window is covered with a phosphor layer. Light emitted directly from the LED light source is first transmitted to the light guiding device and then guided by the light guiding device towards the emitting window to evenly excite the phosphor layer.Type: GrantFiled: April 9, 2013Date of Patent: August 18, 2015Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: Chung-Min Chang, Chien-Lin Chang-Chien, Hsuen-Feng Hu