Patents by Inventor Chien-Ming Chiu
Chien-Ming Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136546Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Inventors: Hung-Hsien Ku, Shang-Qing Zhuang, Ning-Yih Hsu, Chien-Hong Lin, Han-Jou Lin, Yi-Hsin Hu, Po-Yen Chiu, Yao-Ming Wang
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Patent number: 11965522Abstract: An impeller includes a hub and a plurality of blades. The blades are arranged around the hub, and each blade includes a leading edge, a blade tip, a root portion, a trailing edge, a windward side and a leeward side. The windward side including a first turning point and a second turning point, a first vertical height difference is formed from the blade tip to the first turning point, and a second vertical height difference is formed from the first turning point to the second turning point, and the first vertical height difference is greater than the second vertical height difference. The impeller apparently reduces the noise.Type: GrantFiled: January 28, 2022Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Pei-Han Chiu, Chien-Ming Lee, Chung-Yuan Tsang, Chao-Fu Yang
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Publication number: 20220220644Abstract: A warp scheduling method includes: storing plural of first warps issued to a streaming multiprocessor in an instruction buffer module; marking plural of second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling the read/storage unit stall cycle in each time interval to obtain a read/storage unit stall cycle proportion; comparing the read/storage unit stall cycle proportion with the stall cycle threshold, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; issuing the second warps from the instruction buffer module to a corresponding one of the processing modules for execution.Type: ApplicationFiled: April 12, 2021Publication date: July 14, 2022Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Chung-ho CHEN, Chien-ming CHIU, Yu-hsiang WANG
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Patent number: 10867963Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.Type: GrantFiled: March 14, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20200294965Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10127883Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.Type: GrantFiled: June 14, 2016Date of Patent: November 13, 2018Assignee: MEDIATEK INC.Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
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Publication number: 20180095522Abstract: Concepts and examples pertaining to scenario-based policy for performance and power management in an electronic apparatus are described. A processor of an electronic apparatus determines whether an application currently executed on the electronic apparatus is of a predefined type of applications. The processor controls one or more aspects of operations of the electronic apparatus in executing the application responsive to the determining indicating the application being of the predefined type of applications.Type: ApplicationFiled: July 12, 2017Publication date: April 5, 2018Inventors: Po-hua Huang, Chien-Ming Chiu
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Publication number: 20170116951Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.Type: ApplicationFiled: June 14, 2016Publication date: April 27, 2017Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
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Patent number: 9478480Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.Type: GrantFiled: November 14, 2014Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Publication number: 20150069580Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8896136Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.Type: GrantFiled: June 30, 2010Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8841773Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.Type: GrantFiled: September 10, 2012Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
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Patent number: 8466059Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.Type: GrantFiled: March 30, 2010Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
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Publication number: 20130001799Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
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Publication number: 20120001337Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Publication number: 20110241217Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
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Publication number: 20070012335Abstract: A multi-step cleaning procedure cleans phase shift photomasks and other photomasks and Mo-containing surfaces. In one embodiment, vacuum ultraviolet (VUV) light produced by an Xe2 excimer laser converts oxygen to ozone that is used in a first cleaning operation. The VUV/ozone clean may be followed by a wet SC1 chemical clean and the two-step cleaning procedure reduces phase-shift loss and increases transmission. In another embodiment, the first step may use other means to form a molybdenum oxide on the Mo-containing surface. In another embodiment, the multi-step cleaning operation provides a wet chemical clean such as SC1 or SPM or both, followed by a further chemical or physical treatment such as ozone, baking or electrically ionized water.Type: ApplicationFiled: July 18, 2005Publication date: January 18, 2007Inventors: Hsiao Chang, Tsun-Cheng Tang, Fei-Gwo Tsai, Tzu-Li Lee, Chien-Ming Chiu, Jang Lee, Yih-Chen Su, Chih-Cheng Lin, Tung Kang, Hung Hsieh
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Publication number: 20050124151Abstract: A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.Type: ApplicationFiled: December 4, 2003Publication date: June 9, 2005Inventors: Yi-Lung Cheng, Ren-Haur Liu, Cheng-Hsiung Liu, Ying-Lang Wang, Hway-Chi Lin, Chien-Ming Chiu