Patents by Inventor Chien-Ming Chiu

Chien-Ming Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12147811
    Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 19, 2024
    Inventors: Chung-ho Chen, Chien-ming Chiu, Yu-hsiang Wang
  • Publication number: 20220220644
    Abstract: A warp scheduling method includes: storing plural of first warps issued to a streaming multiprocessor in an instruction buffer module; marking plural of second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling the read/storage unit stall cycle in each time interval to obtain a read/storage unit stall cycle proportion; comparing the read/storage unit stall cycle proportion with the stall cycle threshold, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; issuing the second warps from the instruction buffer module to a corresponding one of the processing modules for execution.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 14, 2022
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chung-ho CHEN, Chien-ming CHIU, Yu-hsiang WANG
  • Patent number: 10867963
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20200294965
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10127883
    Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
  • Publication number: 20180095522
    Abstract: Concepts and examples pertaining to scenario-based policy for performance and power management in an electronic apparatus are described. A processor of an electronic apparatus determines whether an application currently executed on the electronic apparatus is of a predefined type of applications. The processor controls one or more aspects of operations of the electronic apparatus in executing the application responsive to the determining indicating the application being of the predefined type of applications.
    Type: Application
    Filed: July 12, 2017
    Publication date: April 5, 2018
    Inventors: Po-hua Huang, Chien-Ming Chiu
  • Publication number: 20170116951
    Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.
    Type: Application
    Filed: June 14, 2016
    Publication date: April 27, 2017
    Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
  • Patent number: 9478480
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20150069580
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Application
    Filed: November 14, 2014
    Publication date: March 12, 2015
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8841773
    Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
  • Patent number: 8466059
    Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: June 18, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
  • Publication number: 20130001799
    Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
  • Publication number: 20120001337
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20110241217
    Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
  • Publication number: 20070012335
    Abstract: A multi-step cleaning procedure cleans phase shift photomasks and other photomasks and Mo-containing surfaces. In one embodiment, vacuum ultraviolet (VUV) light produced by an Xe2 excimer laser converts oxygen to ozone that is used in a first cleaning operation. The VUV/ozone clean may be followed by a wet SC1 chemical clean and the two-step cleaning procedure reduces phase-shift loss and increases transmission. In another embodiment, the first step may use other means to form a molybdenum oxide on the Mo-containing surface. In another embodiment, the multi-step cleaning operation provides a wet chemical clean such as SC1 or SPM or both, followed by a further chemical or physical treatment such as ozone, baking or electrically ionized water.
    Type: Application
    Filed: July 18, 2005
    Publication date: January 18, 2007
    Inventors: Hsiao Chang, Tsun-Cheng Tang, Fei-Gwo Tsai, Tzu-Li Lee, Chien-Ming Chiu, Jang Lee, Yih-Chen Su, Chih-Cheng Lin, Tung Kang, Hung Hsieh
  • Publication number: 20050124151
    Abstract: A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 9, 2005
    Inventors: Yi-Lung Cheng, Ren-Haur Liu, Cheng-Hsiung Liu, Ying-Lang Wang, Hway-Chi Lin, Chien-Ming Chiu