Alignment mark and method of formation
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
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This application is a continuation of U.S. patent application Ser. No. 12/827,563, filed on Jun. 30, 2010, entitled “Alignment Mark and Method of Formation,” which disclosure is incorporated herein by reference in its entirety.
BACKGROUNDIn semiconductor processing, the formation of structures and devices generally include the sequential formation of one layer of material or composition of materials over another layer. These layers are commonly etched or doped using photolithography techniques to direct the areas where the layers are etched or doped. For example, the formation a source/drain region of a transistor may include forming a photoresist layer over the semiconductor substrate in which a source/drain region is to be formed, exposing the photoresist layer to light such that the volume of photoresist above the area where the source/drain region is to be formed is removed, and doping the semiconductor substrate using the photoresist to prevent unexposed areas from being doped. Further, a contact to the source/drain region may include depositing an insulating layer over the semiconductor substrate, forming a photoresist over the insulating layer, exposing the photoresist to light such that a volume of photoresist over the source/drain region is removed, etching the insulating layer using the photoresist as a mask, and depositing a metal.
The integrity of the devices formed using these photolithography techniques is therefore dependent upon proper alignment of features from one layer to another. In the example above, the contact must be aligned with the source/drain region. Misalignment between these layers may prevent a device from being operational.
The semiconductor processing field has developed alignment marks to allow higher precision in aligning photolithographic processes between layers. Alignment marks allow for the measurement of the placement of a wafer upon which processing has proceeded. Based on a measurement, a stepper may move or modify the position of the wafer to help enable better alignment of the photolithography processes.
For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
Embodiments will be described with respect to a specific context, namely an alignment mark formed during the processing of a die for a stacked device. Other embodiments may also be applied, however, to an interposer or another structure where an alignment mark is used during processing.
Further, the front side of the substrate 100 has been attached by adhesive 110 to a carrier 112 for back side processing. Generally, the carrier 112 provides temporary mechanical and structural support during subsequent processing steps. In this manner, damage to the substrate 100 may be reduced or prevented. The carrier 112 may comprise, for example, glass, silicon oxide, aluminum oxide, and the like. The adhesive 110 may be any suitable adhesive, such as an ultraviolet (UV) glue, which loses its adhesive property when exposed to UV lights. It should be noted that reference numbers 104 through 112 are not explicitly identified in
In
The method as depicted in
Further, the front side of the substrate 200 has been attached by adhesive 210 to a carrier 212 for back side processing. Generally, the carrier 212 provides temporary mechanical and structural support during subsequent processing steps. In this manner, damage to the substrate 200 may be reduced or prevented. The carrier 212 may comprise, for example, glass, silicon oxide, aluminum oxide, and the like. The adhesive 210 may be any suitable adhesive, such as an ultraviolet (UV) glue, which loses its adhesive property when exposed to UV lights. It should be noted that reference numbers 204 through 212 are not explicitly identified in
In
The method as depicted in
Embodiments may prevent diffusion of metal in the alignment mark. The isolation layer(s) may form a barrier layer to prevent a metal, such as copper, from diffusing into the substrate in the embodiments. By preventing diffusion, devices and structures formed in the substrate are less likely to be inoperable because of shorting or other problems that may be caused by diffusion of the metal in the alignment mark.
Also, the structures and processes of the embodiments discussed above may provide increased throughput from a process flow. Further, they may ease stress and strain in the thinned substrate because of an improved process flow, such as because of lower temperatures being used.
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
Another embodiment is a structure having an alignment mark. The structure comprises a substrate comprising a through substrate via (TSV), the TSV extending from a front surface of the substrate to a back surface of the substrate; an isolation layer over the back surface of the substrate, the isolation layer having a cavity; and a conductor positioned in the cavity, the isolation layer being disposed between the conductor and the substrate in the cavity.
A yet further embodiment is a method for forming a stacked device. The method comprises providing a substrate having a through substrate via (TSV) protruding from a back side; forming an isolation layer over the back side of the substrate, the isolation layer having a recess; and forming a conductive layer in the recess, the isolation layer being disposed between the conductive layer and the substrate in the recess.
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A structure comprising:
- a substrate having a surface, a through via being in the substrate and protruding from the surface of the substrate;
- an isolation layer on the surface of the substrate, the isolation layer defining a first recess having isolation sidewalls and an isolation bottom surface;
- a first conductive layer in the first recess conformally lining the isolation sidewalls and the isolation bottom surface; and
- a second conductive layer over and conformal to the first conductive layer, the second conductive layer having a second composition different from a first composition of the first conductive layer.
2. The structure of claim 1, wherein the substrate comprises a second recess extending from the surface into the substrate, the first recess being in the second recess, the isolation layer conformally lining the second recess to define the first recess in the second recess.
3. The structure of claim 1, wherein the first recess does not extend into the substrate.
4. The structure of claim 1, wherein the isolation layer comprises a first sublayer and a second sublayer on the first sublayer, the first sublayer having a different composition from the second sublayer.
5. The structure of claim 4, wherein the first sublayer conformally lines a second recess in the substrate extending from the surface of the substrate, and the second sublayer conformally lines the first sublayer in the second recess, the second sublayer defining the first recess, surfaces of the second sublayer being the isolation sidewalls and the isolation bottom surface.
6. The structure of claim 4, wherein the first recess is through the second sublayer, surfaces of the second sublayer being the isolation sidewalls, and a surface of the first sublayer being the isolation bottom surface.
7. The structure of claim 1, wherein the conductive layer lines at least a portion of the isolation layer outside of the first recess.
8. The structure of claim 1, wherein the conductive layer is electrically insulated through the first recess.
9. A structure comprising:
- a substrate having a surface, a through via being in the substrate and protruding from the surface of the substrate, the substrate having a recess extending from the surface to a depth in the substrate;
- an isolation layer on the surface of the substrate and conformally lining sidewalls of the recess, a bottom surface of the recess, and sidewalls of an upper portion of the through via protruding from the surface of the substrate, wherein an upper surface of the isolation layer is level with an upper surface of the through via distal the substrate; and
- a conductive material on the isolation layer and in the recess.
10. The structure of claim 9, wherein the conductive material conformally lines the isolation layer in the recess.
11. The structure of claim 9, wherein the conductive material lines at least a portion of the isolation layer outside of the recess.
12. The structure of claim 9, wherein the isolation layer comprises a first sublayer and a second sublayer on the first sublayer, the first sublayer having a different composition from the second sublayer.
13. The structure of claim 12, wherein the first sublayer conformally lines the recess in the substrate, and the second sublayer conformally lines the first sublayer in the recess.
14. The structure of claim 9, wherein the conductive material is electrically insulated through the recess.
15. A structure comprising:
- a substrate having a surface, a through via formed in an opening in the substrate and protruding from the surface of the substrate, sidewalls of the opening in the substrate contacting the through via;
- an isolation layer on the surface of the substrate, the isolation layer defining a first recess having isolation sidewalls that extend to and contact an isolation bottom surface, the isolation layer having a first sublayer and a second sublayer on the first sublayer, the first sublayer having a different composition from the second sublayer; and
- a conductive layer in the first recess having a substantially same thickness throughout the conductive layer along and in respective directions perpendicular to the isolation sidewalls and the isolation bottom surface.
16. The structure of claim 15, wherein the first sublayer conformally lines a second recess in the substrate extending from the surface of the substrate, and the second sublayer conformally lines the first sublayer in the second recess, the second sublayer defining the first recess, surfaces of the second sublayer being the isolation sidewalls and the isolation bottom surface.
17. The structure of claim 15, wherein the first recess is through the second sublayer, surfaces of the second sublayer being the isolation sidewalls, and a surface of the first sublayer being the isolation bottom surface.
18. The structure of claim 15, wherein the conductive layer is electrically insulated through the first recess.
19. The structure of claim 15, wherein the through via comprises a liner layer, a diffusion barrier layer, an adhesion layer, or combinations thereof.
20. The structure of claim 15, wherein the conductive layer comprises a first sublayer and a second sublayer on the first sublayer, the first sublayer having a different composition from the second sublayer.
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Type: Grant
Filed: Nov 14, 2014
Date of Patent: Oct 25, 2016
Patent Publication Number: 20150069580
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Chen-Yu Tsai (Zhongli), Shih-Hui Wang (Zhonghe), Chien-Ming Chiu (Hsin-Chu), Chia-Ho Chen (Zhubei), Fang Wen Tsai (Hsin-Chu), Weng-Jin Wu (Hsin-Chu), Jing-Cheng Lin (Hsin-Chu), Wen-Chih Chiou (Zhunan Township), Shin-Puu Jeng (Hsin-Chu), Chen-Hua Yu (Hsin-Chu)
Primary Examiner: Hoang-Quan Ho
Application Number: 14/542,317
International Classification: H01L 23/544 (20060101); H01L 23/48 (20060101); H01L 21/683 (20060101); H01L 21/306 (20060101); H01L 21/768 (20060101);