Abstract: A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.

Abstract: The present invention relates to a driving method for cholesteric liquid crystal display. A plurality of pixels of the display are controlled by a plurality of row drivers and a plurality of column drivers. According to the method of the invention, firstly, a DC input voltage or a non-symmetric AC input voltage is applied to the row drivers and the column drivers so that the voltage of the pixel is larger than a withstand voltage of the drivers. Then, an initial column signal and an initial row signal are respectively supplied by the corresponding column driver and row driver so as to initialize the corresponding pixel. The polarity of the initial column signal is different from that of the initial row signal. Because the initial row signal minus the initial column signal equals the signal of the pixel, the amplitude of the signal applied to the pixel can be increased.

Abstract: A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: A display method for driving a color-sequential display of an electronic device is provided. When the electronic device is not at low power mode, a first image is displayed first by using a second color data and a first color data of the first image sequentially to drive the display. Next, a second image is displayed by using a second color data and a third color data of the second image sequentially to drive the display. When the electronic device is at low power mode, the respective luminance of the first and the second images are obtained. Then, the respective luminance of the first image and the second image are sequentially used to drive the display.

Abstract: The invention relates to a reset device for a scan driver. The scan driver is used for driving a control circuit of a display. The reset device comprises: a first input terminal, a second input terminal and a reset circuit. The first input terminal receives a first input voltage. After the first input voltage inputs to the first input terminal, the second input terminal receives a second input voltage. The second input voltage has a temporary section and a stable section. At the stable section, the second input voltage is larger than the first input voltage. When the first input terminal receives the first input voltage, the reset circuit outputs a reset signal to the scan driver. When the second input voltage is larger than a threshold value at the temporary section, the reset circuit clears the reset signal. According to the reset device of the invention, the scan driver maintains at a reset state so as to prevent that outputs of the scan driver to be at high level at the same time of supplying power.

Abstract: A single polar driving method for a cholesteric liquid crystal display. The method comprises the steps of selecting the pixels by applying a first signal switching between a ground and a first level to the common line of the selected pixels, driving the selected pixels into a reflecting state by applying a second signal out of phase with the first signal and that switches between a second and third levels to the segment lines thereof, driving the selected pixels into a transparent state by applying a third signal in phase with the first signal and that switches between the second and third levels to the segment lines thereof, and deselecting the pixels by applying a fourth signal fixed at a fourth level to the common lines thereof.

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract: A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.

Abstract: A dynamic CMOS level shifter circuit apparatus in a digital electronic system is disclosed for shifting a signal of a first logic family at a first lower voltage level to a second higher voltage level for a second logic family. The shifter circuit apparatus comprises a first transistor pair that has a first PMOS and a first NMOS transistor connected in series; a second transistor pair that has a second PMOS and a second NMOS transistor connected in series; and a power-down control PMOS transistor. The first and second transistor pairs are connected in parallel, and the parallel connection is connected in series with the power-down control PMOS transistor across the power and ground level of the system. The node at which the drain terminals of the transistors of the first transistor pair is connected together is also connected to the gate of the second PMOS transistor.

Abstract: The present invention relates to a driving method for cholesteric liquid crystal display. A plurality of pixels of the display are controlled by a plurality of row drivers and a plurality of column drivers. According to the method of the invention, firstly, a DC input voltage or a non-symmetric AC input voltage is applied to the row drivers and the column drivers so that the voltage of the pixel is larger than a withstand voltage of the drivers. Then, an initial column signal and an initial row signal are respectively supplied by the corresponding column driver and row driver so as to initialize the corresponding pixel. The polarity of the initial column signal is different from that of the initial row signal. Because the initial row signal minus the initial column signal equals the signal of the pixel, the amplitude of the signal applied to the pixel can be increased.

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Abstract: A single polar driving method for a cholesteric liquid crystal display. The method comprises the steps of selecting the pixels by applying a first signal switching between a ground and a first level to the common line of the selected pixels, driving the selected pixels into a reflecting state by applying a second signal out of phase with the first signal and that switches between a second and third levels to the segment lines thereof, driving the selected pixels into a transparent state by applying a third signal in phase with the first signal and that switches between the second and third levels to the segment lines thereof, and deselecting the pixels by applying a fourth signal fixed at a fourth level to the common lines thereof.

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.