Abstract: The present invention relates to an organic light emitting diode, comprising: a first electrode; an organic material layer which comprises a hole transport layer, an electron transport layer and an light emitting layer, wherein the hole transport layer may be interposed between the first electrode and the light emitting layer, and the light emitting layer may be interposed between the hole transport layer and the electron transport layer; a second electrode which is disposed on the organic material layer; and a carrier conversion layer which may be interposed between the first electrode and the hole transport layer or between the second electrode and the electron transport layer; wherein the carrier conversion layer has a thickness of 10 nm to 200 nm.

Abstract: A power semiconductor component includes a semiconductor substrate, a MOS layer, a N-type buffer layer, a P-type injection layer, a backside trench layer and a collector metal layer. The MOS layer is formed on a first surface of the semiconductor substrate for defining a N-type high-resistance layer. The N-type buffer layer is formed on the second surface through ion implanting. The P-type injection layer is formed on the N-type buffer layer through ion implanting and at least one time of ion laser annealing. The backside trench layer is formed on the P-type injection layer and partial N-type buffer layer. The collector metal layer is formed on the P-type injection layer and the backside trench layer, so the collector metal layer, the P-type injection layer and the N-type buffer layer are shorted for forming a structure of a reverse diode in parallel, thereby reducing the area and the cost of encapsulation.

Abstract: An organic light-emitting diode (OLED) display panel is provided. The OLED display panel includes a pixel. The pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting unit and a second light emitting unit. The first light emitting unit is used for emitting a first color light. The second light emitting unit is used for emitting a second color light. The second sub-pixel includes a third light emitting unit and a fourth light emitting unit. The third light emitting unit is used for emitting a third color light. The fourth light emitting unit is used for emitting a fourth color light. The combination of the first color light and the second color light is different from the combination of the third color light and the fourth color light.

Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.

Abstract: The present invention relates to an organic light emitting diode, comprising: a first electrode; an organic material layer which comprises a hole transport layer, an electron transport layer and an light emitting layer, wherein the hole transport layer may be interposed between the first electrode and the light emitting layer, and the light emitting layer may be interposed between the hole transport layer and the electron transport layer; a second electrode which is disposed on the organic material layer; and a carrier conversion layer which may be interposed between the first electrode and the hole transport layer or between the second electrode and the electron transport layer; wherein the carrier conversion layer has a thickness of 10 nm to 200 nm.

Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.

Abstract: A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance.

Abstract: A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.

Abstract: A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.

Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.

Abstract: A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for blocking ions from diffusing into the epitaxial layer, and a deposition layer formed on the ion barrier layer. Thereby, the deep trench of the super-junction device is formed by performing an etch process on the epitaxial layer via the hard mask structure. The hard mask structure can effectively prevent ions from diffusing into the epitaxial layer, so as to avoid unusual electrical property.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.

Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.