Abstract: A gate driver includes a gate driving main circuit and a power sequence control circuit. The gate driving main circuit disposed between an operating voltage and ground is coupled to a first gate voltage and a second gate voltage. The operating voltage is higher than ground and first gate voltage is higher than second gate voltage. The power sequence control circuit includes first-type transistors, a second-type transistor, a transistor and a judging circuit. The first-type transistors are coupled in series between first gate voltage and a first node and their gates are coupled to a second node. The second-type transistor is coupled between first node and second gate voltage and its gate is coupled to second node. The transistor is coupled between first gate voltage and gate driving main circuit and its gate is coupled to first node. The judging circuit generates an output signal to second node.

Abstract: A gate driver includes a gate driving main circuit and a power sequence control circuit. The gate driving main circuit disposed between an operating voltage and ground is coupled to a first gate voltage and a second gate voltage. The operating voltage is higher than ground and first gate voltage is higher than second gate voltage. The power sequence control circuit includes first-type transistors, a second-type transistor, a transistor and a judging circuit. The first-type transistors are coupled in series between first gate voltage and a first node and their gates are coupled to a second node. The second-type transistor is coupled between first node and second gate voltage and its gate is coupled to second node. The transistor is coupled between first gate voltage and gate driving main circuit and its gate is coupled to first node. The judging circuit generates an output signal to second node.

Abstract: A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level. In one example, the total number of the transistors needed by the level shifter is much fewer than that of the prior art, and additional voltage sources are not needed to provide middle voltages. The manufacturing cost of the exemplary level shifter can be reduced and the signal level shifting efficiency of multi-power domain can be enhanced.

Abstract: A source driver pre-charging apparatus including a data detection module, a determining module, and a pre-charging module is disclosed. The data detection module captures a first most significant bit having N bits in a current data and a second most significant bit having N bits in a former data and compares them to generate a compared result. N is a positive integer larger than or equal to 2. The determining module judges whether any data is transited from a first grey-level region to a second grey-level region between the former data and the current data and at least one other grey-level region is existed between the first grey-level region and the second grey-level region. If the judgment result of the determining module is yes, the pre-charging module performs a pre-charging action on an output voltage of a source driver.

Abstract: A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level. In one example, the total number of the transistors needed by the level shifter is much fewer than that of the prior art, and additional voltage sources are not needed to provide middle voltages. The manufacturing cost of the exemplary level shifter can be reduced and the signal level shifting efficiency of multi-power domain can be enhanced.

Abstract: A source driver pre-charging apparatus including a data detection module, a determining module, and a pre-charging module is disclosed. The data detection module captures a first most significant bit having N bits in a current data and a second most significant bit having N bits in a former data and compares them to generate a compared result. N is a positive integer larger than or equal to 2. The determining module judges whether any data is transited from a first grey-level region to a second grey-level region between the former data and the current data and at least one other grey-level region is existed between the first grey-level region and the second grey-level region. If the judgment result of the determining module is yes, the pre-charging module performs a pre-charging action on an output voltage of a source driver.

Abstract: A driving apparatus applied in a liquid crystal display are disclosed. Its first channel includes a first latching module, a first level-shifting module, a P-type digital/analog converting module, a first R2R module, and a P-type amplifying module, the second channel includes a second latching module, a second level-shifting module, a N-type digital/analog converting module, a second R2R module, and a N-type amplifying module. The P-type digital/analog converting module and N-type digital/analog converting module are selectively coupled to the first R2R module or the second R2R module. The first latching module receives a first digital signal and the first latching module outputs a first analog signal corresponding to the first digital signal. The second latching module receives a second digital signal and the second latching module outputs a second analog signal corresponding to the second digital signal.

Abstract: A driving apparatus applied in a liquid crystal display are disclosed. Its first channel includes a first latching module, a first level-shifting module, a P-type digital/analog converting module, and a first R2R module, the second channel includes a second latching module, a second level-shifting module, a N-type digital/analog converting module, and a second R2R module. The P-type digital/analog converting module and N-type digital/analog converting module are selectively coupled to the first R2R module or the second R2R module. The first latching module receives a first digital signal and the first latching module outputs a first analog signal corresponding to the first digital signal. The second latching module receives a second digital signal and the second latching module outputs a second analog signal corresponding to the second digital signal.

Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.

Abstract: A driving method is disclosed, and the driving method is applied into a liquid crystal display apparatus. The driving method includes steps as follows: receiving an original display data; rearranging the original display data to a new display data according to at least one scan driving mode; adjusting sequence of scan driving corresponding to the scan driving mode according to a sequence signal; transmitting the new display data to a display panel through data line, wherein sequence of the original display data corresponds to sequence of scan driving before adjusting, and sequence of the new display data corresponds to sequence of scan driving after adjusting according to the scan driving mode.

Abstract: A display includes a panel, a timing controller, and a source driver. A method for driving the display includes the steps of sending a transfer signal asserted for a first period to the source driver initially at a line period; sending a driving control signal asserted for an asserted period to the source driver by the timing controller initially at a line period, utilizing a large driving capability of the source driver to drive the panel during the asserted period within the line period, and utilizing a small driving capability of the source driver to drive the panel beyond the asserted period within the line period.

Abstract: A driving method is disclosed, and the driving method is adopted to a liquid crystal display apparatus. The driving method includes steps as follows: receiving an original display data; rearranging the original display data to a new display data according to at least a scan driving mode; adjusting a sequence of scan driving so as to correspond to the scan driving mode according to a control signal; transmitting a new display data to a display panel through a data line, wherein the sequence of the original display data corresponds to the sequence of scan driving before adjusting, and a sequence of the new display data corresponds to the sequence of scan driving after adjusting according to the scan driving mode.

Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.

Abstract: A source driver for driving a display panel and including a protection unit, a bias voltage generation unit and a buffer is provided. The protection unit detects a characteristic parameter of the source driver, and generates a switching signal according to a detection result. The bias voltage generation unit determines whether or not to provide a bias voltage according to the switching signal. The buffer is operated in the bias voltage so as to drive pixels in the display panel.

Abstract: A display controlling system utilized in a display, such as an LCD, includes a plurality of data lines and a plurality of source drivers. The source drivers receive a plurality of transfer pulse signals, each of which corresponds to one of the source drivers, and drive the corresponding data lines upon receiving the corresponding transfer pulse signal, wherein the transfer pulse signals are not all identical. The transfer pulse signal can be produced by the timing controller of the display, or the transfer pulse information required for generating the transfer pulse signals can be embedded in the source data to be delivered to the source drivers that generate the transfer pulse signals after obtaining the transfer pulse information. The transfer pulse signal lines between the timing controller and the source drivers can therefore be removed.

Abstract: A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal.

Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: An image driver includes an adjustment signal module, a multiplexer, and a conversion module. The adjustment module generates at least a first adjustment signal and a second adjustment signal. The multiplexer is connected to the adjustment signal module and selectively outputs one of the adjustment signals. The conversion module includes a plurality of conversion units, wherein each of the conversion units receives the selected adjustment signal and generates a driving signal based on the adjustment signal received.

Abstract: A source driver adapted to drive a plurality of data lines on a display panel is disclosed. The source driver includes a first output buffer, a second output buffer, a multiplexer, and a first regulating unit. The first and the second output buffers respectively enhance transmission intensities of a first and a second pixel signals. The first regulating unit regulates a slew rate of the first pixel signal outputted from the first output buffer to match a slew rate of the second pixel signal outputted from the second output buffer. The multiplexer coupled to the regulating unit selectively transmits the first and the second pixel signals to one of the odd data lines and one of the even data line, or to the one of the even data lines or the one of the odd data lines, according to a control signal.