Patents by Inventor Chien-Ru Chen
Chien-Ru Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7772912Abstract: A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.Type: GrantFiled: November 13, 2007Date of Patent: August 10, 2010Assignee: Himax Technologies LimitedInventors: Yu-Jen Yen, Wen-Teng Fan, Chien-Ru Chen
-
Publication number: 20100164926Abstract: A source driver adapted to drive a plurality of data lines on a display panel is disclosed. The source driver includes a first output buffer, a second output buffer, a multiplexer, and a first regulating unit. The first and the second output buffers respectively enhance transmission intensities of a first and a second pixel signals. The first regulating unit regulates a slew rate of the first pixel signal outputted from the first output buffer to match a slew rate of the second pixel signal outputted from the second output buffer. The multiplexer coupled to the regulating unit selectively transmits the first and the second pixel signals to one of the odd data lines and one of the even data line, or to the one of the even data lines or the one of the odd data lines, according to a control signal.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Da-Rong Huang, Chien-Ru Chen
-
Publication number: 20100149170Abstract: A display includes a panel, a timing controller, and a source driver. A method for driving the display includes the steps of sending a transfer signal asserted for a first period to the source driver initially at a line period; sending a driving control signal asserted for an asserted period to the source driver by the timing controller initially at a line period, utilizing a large driving capability of the source driver to drive the panel during the asserted period within the line period, and utilizing a small driving capability of the source driver to drive the panel beyond the asserted period within the line period.Type: ApplicationFiled: December 15, 2008Publication date: June 17, 2010Inventors: Da-Rong Huang, Chien-Ru Chen
-
Publication number: 20100045319Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.Type: ApplicationFiled: October 30, 2009Publication date: February 25, 2010Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Tzong-Yau Ku, Chien-Ru Chen, Chin-Tien Chang, Ying-Lieh Chen, Lin-Kai Bu
-
Patent number: 7642800Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.Type: GrantFiled: August 31, 2007Date of Patent: January 5, 2010Assignee: Himax Technologies LimitedInventors: Tzong-Yau Ku, Chien-Ru Chen, Chin-Tien Chang, Ying-Lieh Chen, Lin-Kai Bu
-
Publication number: 20090295762Abstract: A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Wen-Teng Fan, Chien-Ru Chen
-
Patent number: 7605735Abstract: A digital-to-analog converter (DAC) includes an R-2R ladder network, switches, and an operation amplifier (OP) with a feedback resistance, for providing an analog voltage in a positive polarity and a negative polarity. Each of the switches is switched between a connection to the OP and the reference voltage.Type: GrantFiled: December 5, 2007Date of Patent: October 20, 2009Assignee: Himax Technologies LimitedInventors: Ying-Lieh Chen, Chien-Ru Chen, Chuan-Che Lee
-
Publication number: 20090146856Abstract: The present invention provides the voltage generator comprises providing a binary weight digital-to-analog converter (DAC) including an R-2R ladder network, and control switches, and an operation amplifier (OP) with a feedback resistance, and providing a plurality of voltages, from an input of said ladder network, in a positive polarity and a negative polarity, wherein said positive polarity and negative polarity are determined by a reference voltage, and each of said switches is switched between a connection to said OP and said reference voltage.Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Inventors: Ying-Lieh Chen, Chien-Ru Chen, Chuan-Che Lee
-
Publication number: 20090121771Abstract: A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.Type: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Yu-Jen Yen, Wen-Teng Fan, Chien-Ru Chen
-
Publication number: 20090066675Abstract: The present invention provides a programmable digital to analog converter comprises a reference voltage generator for generating a plurality of reference voltages based on a plurality of reference signals respectively, the gamma reference voltage generator comprising: a resistor string comprising a plurality of resistors in serial for providing a plurality of voltages; and a plurality of reference decoders, each receiving said voltages from said resistor string and selectively outputting a reference voltage from said voltages based on the corresponding reference signal, and a data decoder receiving the reference voltages for selectively outputting an analog voltage based on a data signal.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Inventors: Ying-Lieh Chen, Chien-Ru Chen, Chuan-Che Lee
-
Publication number: 20090058438Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Tzong-Yau Ku, Chien-Ru Chen, Chin-Tien Chang, Ying-Lieh Chen, Lin-Kai Bu
-
Publication number: 20080308929Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Chien-Ru Chen, Ying-Lieh Chen
-
Publication number: 20080303771Abstract: A display and a two step driving method thereof are provided. The method includes: converting an image signal to a corresponding data driving voltage by using a driver; providing a pre-driving voltage by using a voltage generator; and finally, driving the display panel by using the pre-driving voltage and data driving voltage orderly during a horizontal synchronizing period. A display includes a display panel, a voltage generator, and a driver. The display panel also includes at least one data line. The voltage generator outputs a pre-driving voltage to the data line of the display. The driver outputs a data driving voltage to the data line according to an image signal, in which the data line receives the pre-driving voltage and the data driving voltage orderly during the horizontal synchronizing period.Type: ApplicationFiled: August 15, 2007Publication date: December 11, 2008Applicants: HIMAX TECHNOLOGIES LIMITED, CHI MEI OPTOELECTRONICS CORPORATIONInventors: Ying-Lieh Chen, Lin-Kai Bu, Chien-Ru Chen, Chih-Hsing Chang, Wen-Tsung Lin, Yung-Yu Tsai, Yung-Li Huang
-
Publication number: 20080291147Abstract: The present invention provides a liquid crystal display comprising a display panel, a plurality of gate drivers sequentially enabling rows of pixels of the display panel, a plurality of source drivers outputting a plurality of driving signals to the enabled row of the pixels of the display panel, and a timing controller outputting each of a plurality of start pulses to all the source drivers and sequentially enabling the source drivers so that each source driver respectively receives one of the start pulses, wherein each the source drivers latch a plurality of image signals when receiving one of the start pulses.Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Wen-Teng FAN, Chien-Ru CHEN, Ying-Lieh CHEN
-
Publication number: 20080278090Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.Type: ApplicationFiled: August 7, 2007Publication date: November 13, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Ying Lieh Chen, Kai Lan Chuang, Tsung Yu Wu, Chien Ru Chen, Chin Tien Chang, Chuan Che Lee, Wen Teng Fan
-
Patent number: 7449916Abstract: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.Type: GrantFiled: May 3, 2006Date of Patent: November 11, 2008Assignee: Himax Technologies LimitedInventors: Chien-Ru Chen, Ying-Lieh Chen, Lin-Kai Bu, Yu-Jui Chang
-
Patent number: 7446568Abstract: An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.Type: GrantFiled: May 29, 2006Date of Patent: November 4, 2008Assignee: Himax Technologies LimitedInventors: Chin-Tien Chang, Chien-Ru Chen, Ying-Lieh Chen
-
Publication number: 20080117190Abstract: First and second bits of pixel values of the display are received, and each of the first and second bits is forwarded through one of data signals. Then, levels of the data signals are shifted, and the forwarded first and second bits are received through the level-shifted data signals to convert the pixel values into analog voltages driving the display. The level-shifted data signals through which the forwarded first and second bits are received are generated in a first and second phase, respectively.Type: ApplicationFiled: November 22, 2006Publication date: May 22, 2008Inventors: Chien-Ru Chen, Ying-Lieh Chen, Lin-Kai Bu
-
Patent number: 7359290Abstract: A power saving method of a chip-on-glass liquid crystal display. The method first (a) wakes up the source drivers of the LCD and (b) transmitting the image data and control signals from the source driver corresponding to the FPC to the farthest waked source drivers, and then switching them to power-saving mode. Steps (b) and (c) are repeated until all the source drivers are switched to power-saving mode.Type: GrantFiled: March 13, 2006Date of Patent: April 15, 2008Assignee: Himax Technologies LimitedInventors: Chien-Ru Chen, Jung-Zone Chen, Ying-Lieh Chen
-
Publication number: 20080030453Abstract: A data transmitting method for inputting a data signal to an electronic device. The data signal includes first and second sets of data, and the electronic device includes first to fourth receiving units and corresponding first to fourth registers. The transmitting method includes the following steps. First, the first and second receiving units are disabled. Then, the first set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers during a first clock cycle of a clock signal. Thereafter, the second set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers while the first set of data stored in the third and fourth registers is inputted to the first and second registers during a second clock cycle of the clock signal.Type: ApplicationFiled: May 29, 2007Publication date: February 7, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Chien-Ru Chen, Ying-Lieh Chen, Lin-Kai Bu